| Patent Number |
Title Of Patent |
Date Issued |
| RE36934 |
Control device for a hands-free telephone set |
October 31, 2000 |
| A control device for a hands-free telephone set automatically controls microphone and amplifier gains so that a feedback loop has less than unity gain to avoid circuit instability and resultant self-oscillation. An emission channel includes a microphone, a signal compressor and a con |
| RE36749 |
Video signal digital slicing circuit |
June 27, 2000 |
| An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) |
| RE36356 |
Electronic component support for memory card and product obtained thereby |
October 26, 1999 |
| The disclosure relates to memory cards having an electronic component housed in a cavity. The electronic support has a first base made of silicon, with a small thickness (between 50 and 100 microns) and a thicker (between 200 and 300 microns) second base, which is deposited on the first |
| RE36208 |
Housing for containing a fragile element such as a logic circuit |
May 11, 1999 |
| A housing designed to contain a logic circuit (15) comprising two shells (11a, 11b) each including a welding area (17a, 17b) having an appropriate geometry permitting ultrasonic welding, such that when both shells are assembled before a welding phase, they are shifted along a vertical ax |
| RE36183 |
System for rearranging sequential data words from an initial order to an arrival order in a pred |
April 6, 1999 |
| A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p.ltoreq.n) elementary processing units arranged in series. Each unit comprises an input, an output, a |
| RE36090 |
Method and a device for synchronizing a signal |
February 9, 1999 |
| A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if t |
| RE35854 |
Programmable protection circuit and its monolithic manufacturing |
July 21, 1998 |
| A programmable protection circuit comprises three identical units connected between a common point (C) and a first conductor (A), a second conductor (B) and ground (M). Each unit comprises the anti-parallel arrangement of a thyristor (T) and a diode (D), a bipolar transistor (TR) being c |
| RE35483 |
Switching matrix crosspoint |
March 25, 1997 |
| A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current |
| RE35385 |
Method for fixing an electronic component and its contacts to a support |
December 3, 1996 |
| A method for positioning an electronic component and its contacts on a card is disclosed. The electronic component is first of all placed in the cavity of the card, then the electrical contacts are placed on the card and electrically connected to the output terminals by a so-called tape |
| RE35365 |
Squaring circuit for binary numbers |
October 29, 1996 |
| A squaring circuit for a binary number X of n bits x.sub.0 to x.sub.n-1, includes a table of the squares of numbers p constituted by bits x.sub.1 to x.sub.n-2. An adder for adding numbers of 2n-3 bits receives at a first input a number constituted by bit x.sub.n-1, positioned on the left |
| RE35305 |
Amplification circuit with a determined input impedance and various transconductance values |
July 30, 1996 |
| A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an |
| RE34772 |
Voltage generator for generating a stable voltage independent of variations in the ambient tempe |
November 1, 1994 |
| A stable reference voltage generator using a current mirror circuit comprising a primary branch and a secondary branch, is shown and described. A first bipolar transistor (Q1) has its collector connected in series with the primary branch of the current mirror, and a voltage divider b |
| RE34734 |
Integrated digital signal processing circuit for performing cosine transformation |
September 20, 1994 |
| Integrated circuits capable of carrying out transformations of the "cosine transformation" type, used more particularly for the digital processing of images with a view to information compression. The versatile and compact circuit architecture involves dividing a bus into sections separa |
| 7023060 |
Methods for programming read-only memory cells and associated memories |
April 4, 2006 |
| A method for programming a read-only memory cell including a transistor whose source and drain, which have a second type of doping, are formed in a semiconductor substrate with a first type of doping, includes a step of carrying out a contradoping in a region of the source, the region be |
| 6984872 |
Method for fabricating an NPN transistor in a BICMOS technology |
January 10, 2006 |
| The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth |
| 6943592 |
Detector of range of supply voltage in an integrated circuit |
September 13, 2005 |
| The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second ref |
| 6934202 |
Memory circuit with dynamic redundancy |
August 23, 2005 |
| The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that |
| 6914908 |
Multitask processing system |
July 5, 2005 |
| The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the comman |
| 6885174 |
System for providing a regulated voltage to supply a load |
April 26, 2005 |
| The present invention relates to a system for providing a regulated voltage meant to supply a load, including a source for providing a substantially constant current approximately corresponding to the maximum current likely to be surged by the load, and a device receiving the constant cu |
| 6781804 |
Protection of the logic well of a component including an integrated MOS power transistor |
August 24, 2004 |
| The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components b |
| 6674148 |
Lateral components in power semiconductor devices |
January 6, 2004 |
| A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface when it is desired to reduce the |
| 6645803 |
Method for modifying the doping level of a silicon layer |
November 11, 2003 |
| A method for modifying the doping level of a doped silicon layer including the steps of coating the silicon layer with a silicide layer made of a refractory metal, and heating the interface region between the silicon and the silicide to a predetermined temperature. The method may be appl |
| 6633071 |
Contact on a P-type region |
October 14, 2003 |
| The present invention relates to a contacting structure on a lightly-doped P-type region of a semiconductor component, this P-type region being positively biased during the on-state operation of said component, including, on the P region a layer of a platinum silicide, or of a metal |
| 6606609 |
Apparatus and method for operating an integrated circuit |
August 12, 2003 |
| An integrated circuit comprising a logic processor and a fuzzy logic coprocessor is disclosed which processes a plurality of analog inputs. The logic processor and fuzzy logic processor are combined in the form of a single integrated circuit. The integrated circuit accepts a plurality of |
| 6584523 |
Device for organizing the access to a memory bus |
June 24, 2003 |
| This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determin |
| 6580142 |
Electrical control methods involving semiconductor components |
June 17, 2003 |
| A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous |
| 6559409 |
Method for marking integrated circuits with a laser |
May 6, 2003 |
| A method for physically marking, on silicon wafers, of integrated circuits deemed to be defective during a testing step, so as to modify the visual appearance of the surface of these circuits, wherein the marking is done by the exposure of the circuits to a laser beam. The disclosure als |
| 6525582 |
Latch operating with a low swing clock signal |
February 25, 2003 |
| The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output |
| 6525393 |
Semiconductor substrate having an isolation region |
February 25, 2003 |
| A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling |
| 6523121 |
Bus system with a reduced number of lines |
February 18, 2003 |
| In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional s |
| 6480056 |
Network of triacs with gates referenced with respect to a common opposite face electrode |
November 12, 2002 |
| The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains |
| 6434056 |
Set of two memories on the same monolithic integrated circuit |
August 13, 2002 |
| Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose ro |
| 6432789 |
Method of forming a well isolation bipolar transistor |
August 13, 2002 |
| The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a |
| 6430720 |
Functional testing method and circuit including means for implementing said method |
August 6, 2002 |
| The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being |
| 6411155 |
Power integrated circuit |
June 25, 2002 |
| A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous |
| 6396934 |
Analog audio filter for high frequencies |
May 28, 2002 |
| The present invention relates to an active analog filter including a differential amplifier, an output of which provides a filtered signal and a non-inverting input of which is connected to a median potential between supply potentials of the amplifier, a first series association of a fir |
| 6385599 |
Method and apparatus for a fuzzy self-adaptive control system |
May 7, 2002 |
| To resolve a problem of the repairing of an electronic system, a machine will undergo a learning stage during the replacement of a part of the machine. This learning stage can be monitored manually or automatically on a limited range of variation. During this learning stage, readings are |
| 6380847 |
Control circuit for a vibrating membrane |
April 30, 2002 |
| The present invention relates to a control circuit of a vibrating membrane excited by a solenoid in series with a d.c. supply and a controlled switch. A capacitor is disposed across a series circuit including the solenoid and the switch associated with opening means in the vicinity of a |
| 6376883 |
Bipolar transistor and capacitor |
April 23, 2002 |
| The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base |
| 6373672 |
Static and monolithic current limiter and circuit-breaker component |
April 16, 2002 |
| The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limit |
| 6373311 |
Oscillator and switch-over control circuit for a high-voltage generator |
April 16, 2002 |
| An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop |
| 6349111 |
Circuit for allocating a transmission channel on the electric network |
February 19, 2002 |
| The present invention relates to a circuit for allocating a channel to a transmission between at least two modems that use an electric network as a medium for the transmission of a binary data flow. The circuit includes, on the receive side, a device for selecting a channel that is selec |
| 6347308 |
Method for the processing of information by fuzzy logic |
February 12, 2002 |
| In a system of information processing by fuzzy logic, force coefficients are associated with values of variables processed by a fuzzy logic processor. The force coefficients show the degree of urgency with which information sent has to be taken into consideration or indicating the im |
| 6321324 |
Device for putting an integrated circuit into operation |
November 20, 2001 |
| To enable the putting into use of a monolithic integrated circuit comprising a processor and a fuzzy logic coprocessor, both having a single program memory in common, an operation is effected by which, at the time of the initializing of the integrated circuit, a volatile, random-access |
| 6294901 |
Power dimmer |
September 25, 2001 |
| The present invention relates to a power dimmer of a load, powered by an a.c. voltage, of the type including a bidirectional switch associated in series with the load, the switch being normally closed and controllable to be opened upon each halfwave of the a.c. voltage. |
| 6281723 |
Device and method for power-on/power-off checking of an integrated circuit |
August 28, 2001 |
| A checking device to control the power-on or power-off operations in an integrated circuit comprises a voltage reference circuit biased by a bias circuit, and an output stage. The device further comprises a control circuit to activate or deactivate the bias circuit as a function of the |
| 6281722 |
Bias source control circuit |
August 28, 2001 |
| The invention relates to a control circuit for a bias source including a stand-by device and a starting-aid device, with their respective outputs connected to a control input of the bias source, the starting-aid device including a switch to inhibit its operation, controlled by the bias |
| 6279068 |
Set of two memories on the same monolithic integrated circuit |
August 21, 2001 |
| Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose ro |
| 6278868 |
Transceiver circuit including a circuit for measuring the delay introduced by telephone lines |
August 21, 2001 |
| The present invention relates to a master transceiver circuit meant to be coupled by a telephone line to a slave transceiver circuit, the master circuit including a digital phase-locked loop for reconstructing a clock from an incoming bit flow, the phase difference between the reconstruc |
| 6265277 |
Method for making a bipolar transistor for the protection of an integrated circuit against elect |
July 24, 2001 |
| In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantage |
