| Patent Number |
Title Of Patent |
Date Issued |
| 5237485 |
Apparatus and method for improved thermal coupling of a semiconductor package to a cooling plate |
August 17, 1993 |
| A heat sink and method for heat sinking a package containing electronic components is described. The heat sinking is accomplished by use of a cooling plate located beneath a circuit board. The package having leads extending from more than one side of the package is positioned on the |
| 5001547 |
Method and apparatus for improving thermal coupling between a cooling plate of a semiconductor p |
March 19, 1991 |
| A semiconductor component package comprises a metal plate and a synthetic resin housing or body. The plate is formed with an aperture by which it can be secured to a heat sink, generally a metal plate. Around the aperture is a weakened annular portion produced by shearing. When the p |
| 4935790 |
EEPROM memory cell with a single level of polysilicon programmable and erasable bit by bit |
June 19, 1990 |
| The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory. |
| 4926376 |
Method of designing integrated microcomputers and integrated microcomputer with modular structur |
May 15, 1990 |
| The microcomputer is assembled by association of a variable plurality of rectangular functional modules having a fixed first dimension and a variable second dimension. Common busses electrically connect the various modules automatically. |
| 4916085 |
MOS power structure with protective device against overvoltages and manufacturing process theref |
April 10, 1990 |
| A MOS power structure made up of at least one MOS cell with gate electrode, drain electrode, source electrode, well-region and of a bi-polar parasitic transistor provided with a protective device for the gate and drain against overvoltages. The protective device consists of a further bi- |
| 4892836 |
Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage elect |
January 9, 1990 |
| This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region |
| 4892615 |
Method for decontamination of a chamber used in vacuum processes for deposition, etching and/or |
January 9, 1990 |
| A decontamination system for processes for deposition, etching and/or growth of high purity films, particularly applicable to semiconductor technology.After introducing the products concerned with a process into a chamber and after creating a vacuum in the chamber, the chamber is deconta |
| 4890149 |
Integrated device for shielding charge injection into the substrate, in particular in driving ci |
December 26, 1989 |
| This integrated device for shielding injected charges in driving circuits for inductive and/or capacitive loads comprises four integrated structures including a first barrier region with high resistivity which surrounds the buried layer of the epitaxial flyback pocket which may be set at |
| 4888307 |
Method for manufacturing plastic encapsulated semiconductor devices |
December 19, 1989 |
| A method for correctly positioning a metallic plate supporting a semiconductor chip in a mold used for encapsulation, wherein according to a first solution, at least a pair of retractable locating pins are utilized together with a lead connected to the supporting plate. The ends of t |
| 4886982 |
Power transistor with improved resistance to direct secondary breakdown |
December 12, 1989 |
| This power transistor comprises a plurality of elementary transistors, also indicated as "fingers", having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base termi |
| 4874965 |
Circuital device for the power-on reset of digital integrated circuits in MOS technology |
October 17, 1989 |
| A power-on reset circuit for supplying a reset pulse when a supply voltage rises above a preset threshold includes a reference voltage generator connected between the supply voltage and ground for supplying a reference signal having a constant preset value when the supply voltage is grea |
| 4871963 |
Method and apparatus for testing EPROM type semiconductor devices during burn-in |
October 3, 1989 |
| An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the |
| 4868422 |
TTL compatible CMOS logic circuit for driving heavy capacitive loads at high speed |
September 19, 1989 |
| CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters conne |
| 4847896 |
Monolithically integratable telephone circuit for supplying ringing signals to a subscriber's te |
July 11, 1989 |
| A telephone circuit, which may be monolithically integrated, for supplying ringing signals to a subscriber's telephone line and for detecting an off the hook condition during ringing, including a logic control circuit connected to exchange components which control the supply of the ringi |
| 4847811 |
Pre-charging circuit for word lines of a memory system, in particular with programmable cells |
July 11, 1989 |
| A voltage divider is placed between a supply terminal and ground and an intermediate node is connected to the word line to ensure a precharging voltage to the word line which is lower than the supply voltage. The voltage divider is characterized by a precharging transistor included in |
| 4843253 |
Monolithically integratable circuit for the generation of extremely short duration current pulse |
June 27, 1989 |
| A circuit, which may be monolithically integrated, for the generation of current pulses of extremely short duration, includes a differential input structure with first and second PNP transistors. The circuit also includes third, fourth and fifth NPN transistors. The emitter of the third |
| 4839768 |
Protection of integrated circuits from electrostatic discharges |
June 13, 1989 |
| The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectabl |
| 4837464 |
Phase regulation circuit, particularly for horizontal phase regulation in data displays |
June 6, 1989 |
| This circuit comprises a phase-lock stage receiving at the input a reference signal and the synchronism signal EN and generating at the output a triangular signal in phase correlation with the synchronism signal, a rectangular waveform generator receiving at the input the triangular |
| 4829344 |
Electronic semiconductor device for protecting integrated circuits against electrostatic dischar |
May 9, 1989 |
| This electronic semiconductor device for protecting integrated circuits against electrostatic discharges has a minimal bulk, can withstand high damaging voltages and be produced during the same production phases as the integrated circuit to be protected. The device comprises a pair of di |
| 4823316 |
Eeprom memory cell with a single polysilicon level and a tunnel oxide zone |
April 18, 1989 |
| The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor. |
| 4823175 |
Electrically alterable, nonvolatile floating gate memory device |
April 18, 1989 |
| Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer in the "injection" area between the silicon (drain region of the device) and the floating gate has an increased thickness with respect to the thickness of |
| 4821136 |
Power transistor with self-protection against direct secondary breakdown |
April 11, 1989 |
| A power transistor with self-protection against direct secondary breakdown comprises a plurality of elementary transistors having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector |
| 4817012 |
Method for identification of parasitic transistor devices in an integrated structure |
March 28, 1989 |
| In order to identify parasitic transistors in bipolar integrated circuit structures, files relating to the parameters of the simulated circuit are established. These files are then manipulated to establish the operating parameters of the simulated circuit. These operating parameters are |
| 4816702 |
CMOS logic circuit |
March 28, 1989 |
| A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit |
| 4810902 |
Logic interface circuit with high stability and low rest current |
March 7, 1989 |
| An improved logic interface circuit having both a low current drain under rest conditions and a great stability in respect of temperature variations, is based on an original and effective implementation of the so-called bandgap-type voltage reference circuit, according to which the i |
| 4808261 |
Fabrication process for EPROM cells with oxide-nitride-oxide dielectric |
February 28, 1989 |
| The process calls for covering of the dielectric with a thin additional layer of polysilicon which has the function of protecting the dielectric from any defects which would otherwise be introduced from the subsequent masking. |
| 4806501 |
Method for making twin tub CMOS devices |
February 21, 1989 |
| A method is disclosed for making twin tub devices with trench isolation. The trench mask is obtained in a self-aligned manner employing tub masks that define an overlapping region at the trench. In one embodiment, the N-tub mask is defined by patterning resist (4) and polysilicon (3) |
| 4806199 |
(RIE) Plasma process for making metal-semiconductor ohmic type contacts |
February 21, 1989 |
| An improved process of RIE plasma attack of the layer of dielectric material on the surface of wafers of semiconductor material, in correspondence of areas purposely defined by masking, for exposing the underlying semiconductor crystal, in preparation for depositing a layer of materi |
| 4805004 |
Semiconductor device with a planar junction and self-passivating termination |
February 14, 1989 |
| A semiconductor device with a planar junction and self-passivating termination includes: a silicon substrate of one type of conductivity; an epitaxial layer of a second type of conductivity which is opposite to the first type of conductivity, lying on the substrate, so as to form with it |
| 4803381 |
Bias current compensating circuit, particularly for saw-tooth wave generators |
February 7, 1989 |
| This circuit comprises a current source stage connectable to a capacitor which is controlled so as to alternately and periodically charge with the current fed by the source stage and discharge through a switch element, so as to generate a saw-tooth wave voltage. A buffer circuit, with |
| 4801891 |
Differential amplifier utilizing MOS transistors of a single channel polarity |
January 31, 1989 |
| A voltage differential amplifier made with MOS transistors of a single channel polarity and using only two additional transistors besides a differential input pair is exceptionally exempt of problems caused by the normal spread of the parameters of the real components forming the bias |
| 4799021 |
Method and apparatus for testing EPROM type semiconductor devices during burn-in |
January 17, 1989 |
| An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the |
| 4797917 |
Monolithically integratable telephone circuit for supplying ringing signals to a subscriber's te |
January 10, 1989 |
| A telephone circuit, which may be monolithically integrated, for supplying ringing signals to a subscriber's line and for detecting an off the hook condition during ringing includes a circuit for supplying ringing signals coupled to exchange control components for generating a constant f |
| 4797584 |
Power-on reset circuit for MOS logic devices |
January 10, 1989 |
| The power-on reset circuit is adapted to automatically provide a voltage pulse as a positive supply voltage is applied. It essentially comprises:(a) a voltage divider adapted for supplying a reference voltage, comprised of a first and a second series arranged transistors of the normally |
| 4794349 |
Fully differential, CMOS operational power amplifier |
December 27, 1988 |
| A fully differential, CMOS, operational power amplifier, particularly useful as output buffer in monolithic analog subsystems, includes an input differential stage, two gain stages and two output stages. Each output stage may be individually provided with a functional feedback loop and |
| 4792925 |
Eprom memory matrix with symmetrical elementary MOS cells and writing method therefor |
December 20, 1988 |
| The invention provides an EPROM memory matrix and a method of writing to an EPROM memory matrix. Two pluralities of parallel source lines alternate with parallel drain lines while floating gate areas span the source and drain lines and parallel control gate lines are arranged perpendicul |
| 4789644 |
Process for fabrication, by means of epitaxial recrystallization, of insulated-gate field-effect |
December 6, 1988 |
| A process for fabrication, by epitaxial recrystallization, of insulated-gate field-effect transistors with junctions of minimum depth, includes the formation of a layer of polycrystalline silicon on a substrate of monocrystalline silicon in predetermined areas to form source and drai |
| 4786878 |
Low-frequency power amplifier, in particular of the integrated type |
November 22, 1988 |
| The low-frequency integrated amplifier comprises a voltage amplifier stage and two power amplifier stages including power amplifier means driven by the voltage amplifier stage and fedback by means of a respective feedback network dimensioned so that, at the frequency at which the phase s |
| 4786827 |
Antisaturation circuit for integrated PNP transistor with intervention characteristic definable |
November 22, 1988 |
| Described is an antisaturation circuit for an integrated PNP transistor characterized by a comparator circuit comprising two transistors and a current generator whose output current corresponds to a pre-established function, e.g., an exponential function, of the emitter current of said |
| 4783693 |
Driver element for inductive loads |
November 8, 1988 |
| This driver element for inductive loads, specifically DC motors, step motors, solenoids, and the like comprises a transistor bridge, each transistor of the bridge being parallel connected to a respective flyback diode ensuring recirculation of the current on switching the transistors |
| 4782530 |
Non-recursive system for expanding the stereo base of stereophonic acoustic diffusion apparatus |
November 1, 1988 |
| A first and a second input signals, composing a stereophonic pair, are amplified in respective channels, added by adder means in a desired phase relationship, chosen between completely in phase and 180.degree. out of phase, and the sum signal thus produced is processed by a transfer bloc |
| 4782507 |
Monolithically integratable circuit for measuring longitudinal and transverse currents in a two- |
November 1, 1988 |
| A circuit, which may be monolithically integrated, for measuring longitudinal and transverse currents in a two-wire transmission line, includes first and second current mirror circuits of a first type, each having an input branch and first and second output branches. The measuring ci |
| 4782288 |
Method for evaluating processing parameters in the manufacture of semiconductor devices |
November 1, 1988 |
| This method, allowing pointing out of the effects of one manufacture parameter independently from other parameters and phenomena and yielding very high precision in measurement, comprises a first step in which a symmetrical resistive bridge is formed, comprising a pair of test resist |
| 4780624 |
BiMOS biasing circuit |
October 25, 1988 |
| The circuit comprises a first and a second transistor provided with the sources coupled to one end of a supply voltage and the gates coupled to one another, and a third and fourth transistor provided with the sources coupled to the other end of the supply voltage, the gates coupled to on |
| 4780430 |
Process for the formation of a monolithic high voltage semiconductor device |
October 25, 1988 |
| The invention concerns a process for formation of a high voltage monolithic semiconductor device that contains at least one power transistor and an integrated control circuit integrated in a single chip. The device is formed by means of a triple epitaxy which utilizes the same doping age |
| 4774198 |
Self-aligned process for fabricating small DMOS cells |
September 27, 1988 |
| An improved fabrication process for vertical DMOS cells contemplates the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region |
| 4764692 |
MOS power device usable both as an N-channel MOS transistor and as a P-channel MOS transistor |
August 16, 1988 |
| An N-channel power switch is controllable through two inputs by typical control signals for N-channel and P-channel MOS transistors. In the first case the control signal is brought back with unchanged polarity on the gate of the power switch which consequently operates in the peculiar |
| 4761615 |
Voltage repeater circuit with low harmonic distortion for loads with a resistive component |
August 2, 1988 |
| A voltage repeater circuit with low harmonic distortion for loads with a resistive component has first and second N channel MOSFET transistors and a third P channel MOSFET transistor. The first transistor, whose gate electrode forms an input terminal of the circuit, has its drain electro |
| 4756022 |
Integrated circuit for the transmission of telephone signals |
July 5, 1988 |
| An integrated circuit for the transmission of telephone signals is designed so as to be inserted in a speech circuit of a subscriber's telephone set and includes a threshold comparator having first and second input terminals coupled to the terminals of a two-wire telephone line and an |
| 4752722 |
Control circuit with compensation of the anode voltage variation for televisor vertical deflecti |
June 21, 1988 |
| An amplifier stage with variable gain dependent on the anode voltage is interposed between a ramp generator having constant amplitude ramp output voltage and the vertical deflection stage in such a manner as to vary the input voltage of said vertical deflection stage in accordance with a |
