| Patent Number |
Title Of Patent |
Date Issued |
| 7334080 |
Nonvolatile memory with independent access capability to associated buffer |
February 19, 2008 |
| A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volat |
| 7333779 |
PLL circuit and radio communication terminal apparatus using the same |
February 19, 2008 |
| In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation |
| 7333565 |
Semiconductor integrated circuit for communication |
February 19, 2008 |
| An orthogonal modulating circuit for modulating signals of two oscillation frequencies differing in phase by 90.degree. with transmission data (I and Q) is used in common for a plurality of bands, an LC resonance circuit comprising inductances L and a capacitor C is used as the output |
| 7333564 |
High frequency power amplifier circuit |
February 19, 2008 |
| The present invention provides a high frequency power amplifier circuit capable of obtaining sufficient detection output even in a range where a request output power level is low and performing a desired output power control by a control loop with the detection output in a radio comm |
| 7333385 |
Semiconductor memory device having the operating voltage of the memory cell controlled |
February 19, 2008 |
| An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memor |
| 7332966 |
High frequency power amplifier circuit |
February 19, 2008 |
| A high frequency power amplifier circuit includes amplifying devices whose control terminals (gate or base terminals) are supplied with a bias voltage. The high frequency power amplifier circuit keeps constant the bias voltage so that the amplifying devices operate in a saturation re |
| 7332800 |
Semiconductor device |
February 19, 2008 |
| For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an u |
| 7332793 |
Semiconductor device |
February 19, 2008 |
| A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a |
| 7332776 |
Semiconductor device |
February 19, 2008 |
| A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation p |
| 7332757 |
MOSFET package |
February 19, 2008 |
| A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second p |
| 7330995 |
Nonvolatile memory apparatus which prevents destruction of write data caused by power shutdown d |
February 12, 2008 |
| The present invention is directed to suppress data loss caused by power shut-down during a rewriting process and to shorten time required to make a depletion check.A nonvolatile memory apparatus includes a rewritable nonvolatile memory and a card controller. The nonvolatile memory has a |
| 7329575 |
Semiconductor device and semiconductor device manufacturing method |
February 12, 2008 |
| A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions (4) are formed in the upper surface of a semiconductor substrate (1) in a memory formation |
| 7328311 |
Memory controller controlling cashed DRAM |
February 5, 2008 |
| According to the semiconductor device and method of the present invention, because regular cache memories subjected to hit checks are distinguished from spare cache memories not subjected to hit checks, and because sense amplifiers are also used as cache memories, built-in cache memories |
| 7327371 |
Graphic controller, microcomputer and navigation system |
February 5, 2008 |
| Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a |
| 7327014 |
Semiconductor integrated circuit device and process for manufacturing the same |
February 5, 2008 |
| A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern |
| 7326641 |
Semiconductor device and method for manufacturing the same |
February 5, 2008 |
| A semiconductor device which can enhance adhesiveness between a barrier conductive film and an organic insulating film, and prevent film-fall-off, and the manufacturing technique thereof are provided. After a silicon nitride film is formed on the main surface of semiconductor substra |
| 7326627 |
Method of fabricating a semiconductor device with a trench isolation structure and resulting sem |
February 5, 2008 |
| The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expos |
| 7326616 |
Semiconductor integrated circuit device and a method of manufacturing the same |
February 5, 2008 |
| Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a f |
| 7325746 |
Memory card and semiconductor device |
February 5, 2008 |
| An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are divided into two areas |
| 7324397 |
Semiconductor integrated circuit |
January 29, 2008 |
| A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors wh |
| 7324388 |
Nonvolatile memory |
January 29, 2008 |
| A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning |
| 7323901 |
Semiconductor integrated circuit device |
January 29, 2008 |
| A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedan |
| 7323788 |
Semiconductor device and manufacturing method of them |
January 29, 2008 |
| A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a mai |
| 7323781 |
Semiconductor device and manufacturing method thereof |
January 29, 2008 |
| The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having |
| 7323773 |
Semiconductor device |
January 29, 2008 |
| There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smal |
| 7323770 |
Hybrid integrated circuit device, and method for fabricating the same, and electronic device |
January 29, 2008 |
| A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear s |
| 7323741 |
Semiconductor nonvolatile memory device |
January 29, 2008 |
| A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source |
| 7323735 |
Method of manufacturing semiconductor integrated circuit device having capacitor element |
January 29, 2008 |
| In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the |
| 7323381 |
Semiconductor device and manufacturing method thereof |
January 29, 2008 |
| A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (Hf |
| 7323366 |
Manufacturing method of a semiconductor device |
January 29, 2008 |
| A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion |
| 7323097 |
Electroplating method for a semiconductor device |
January 29, 2008 |
| An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating sol |
| 7321525 |
Semiconductor integrated circuit device |
January 22, 2008 |
| The present invention provides a semiconductor integrated circuit device provided with an interface circuit, which has realized speeding-up. A first input circuit inputs a data strobe signal therein, and a second input circuit inputs therein data formed in sync with the timing of a c |
| 7321171 |
Semiconductor integrated circuit device |
January 22, 2008 |
| A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside o |
| 7321152 |
Thin-film transistor and method of fabricating the same |
January 22, 2008 |
| Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source |
| 7320910 |
Semiconductor device |
January 22, 2008 |
| Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate elec |
| 7320482 |
Semiconductor integrated circuit device |
January 22, 2008 |
| The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier |
| 7319730 |
Data communication method and data communication device and semiconductor device |
January 15, 2008 |
| The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding |
| 7319603 |
Semiconductor memory device layout comprising high impurity well tap areas for supplying well vo |
January 15, 2008 |
| A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied throu |
| 7319268 |
Semiconductor device having capacitors for reducing power source noise |
January 15, 2008 |
| A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being elect |
| 7317658 |
Semiconductor integrated circuit and IC card |
January 8, 2008 |
| A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the |
| 7317640 |
Nonvolatile memory with erasable parts |
January 8, 2008 |
| In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress appl |
| 7317634 |
Nonvolatile semiconductor memory device |
January 8, 2008 |
| The programming speed of a nonvolatile semiconductor memory device used as a flash memory is increased as follows. First, second, and third assist gates, a control gate, as well as first and second storage nodes are created over a p-type well. In the course of a programming operation, |
| 7317627 |
Semiconductor integrated circuit with voltage generation circuit, liquid crystal display control |
January 8, 2008 |
| There is to be provided a liquid crystal drive controller with a built-in power supply circuit wherein latch-up is made difficult to arise even if one amplitude level of the segment line drive voltage is set to the ground potential and the levels of other liquid crystal drive voltages |
| 7317461 |
Display drive control device and electric device including display device |
January 8, 2008 |
| In a system including a color liquid crystal panel, a liquid crystal display drive control device for driving the panel, and a microprocessor, the display drive control device of the invention lightens the burden imposed on a microprocessor as well as reduces the power consumption of |
| 7317224 |
Semiconductor device |
January 8, 2008 |
| A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is for |
| 7315649 |
Information recognition device operating with low power consumption |
January 1, 2008 |
| A character recognition device recognizing characters with low power consumption includes a data input unit for entering handwriting data representing a character to be recognized, a character recognition dictionary storing character recognition information required for character rec |
| 7315468 |
Thin film magnetic memory device for conducting data write operation by application of a magneti |
January 1, 2008 |
| A peripheral circuitry is provided adjacent to a memory array and conducts read and write operations from and to the memory array. A power supply voltage line and a ground line for supplying an operating voltage to the peripheral circuitry supply a power supply voltage and a ground volta |
| 7315061 |
Semiconductor device and method of manufacturing the same |
January 1, 2008 |
| An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate |
| 7314830 |
Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt |
January 1, 2008 |
| A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at |
| 7314805 |
Method for fabricating semiconductor device |
January 1, 2008 |
| An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the |
