| Patent Number |
Title Of Patent |
Date Issued |
| 7394706 |
Semiconductor integrated circuit device |
July 1, 2008 |
| A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode |
| 7394697 |
Nonvolatile semiconductor memory device which stores multi-value information |
July 1, 2008 |
| To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit |
| 7394685 |
Nonvolatile memory device with write error suppressed in reading data |
July 1, 2008 |
| A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state |
| 7394143 |
Semiconductor integrated circuit device |
July 1, 2008 |
| Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power sou |
| 7394115 |
Semiconductor integrated circuit device having clock signal transmission line and wiring method |
July 1, 2008 |
| A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal |
| 7393737 |
Semiconductor device and a method of manufacturing the same |
July 1, 2008 |
| A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is |
| 7393731 |
Semiconductor device and method of manufacturing the same |
July 1, 2008 |
| A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating |
| 7392457 |
Memory storage device having a nonvolatile memory and memory controller with error check operati |
June 24, 2008 |
| A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory |
| 7392106 |
Fabrication system and fabrication method |
June 24, 2008 |
| A fabricating method for a system that includes a plurality of processing apparatuses connected to each other by an inter-apparatus transporter and a computer storing managing information of processing and transporting of semiconductor wafers. The processing apparatuses have an interface |
| 7391667 |
Semiconductor integrated circuit |
June 24, 2008 |
| An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are |
| 7391655 |
Data processing system and nonvolatile memory |
June 24, 2008 |
| Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of |
| 7391354 |
Semiconductor integrated circuit |
June 24, 2008 |
| One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter |
| 7391095 |
Semiconductor device |
June 24, 2008 |
| In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole o |
| 7391083 |
Semiconductor device and a method of manufacturing the same |
June 24, 2008 |
| A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the |
| 7390758 |
Method of manufacturing a semiconductor integrated circuit device with elimination of static cha |
June 24, 2008 |
| A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-eliminating the semiconductor substrates before and after |
| 7388777 |
Semiconductor device |
June 17, 2008 |
| A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS.cndot.FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS.cndot.FET for writing data, a MIS.cndot.FE |
| 7388295 |
Multi-chip module |
June 17, 2008 |
| A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically conne |
| 7388256 |
Semiconductor device and a method of manufacturing the same |
June 17, 2008 |
| In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 .mu.m or less, or a trench of 2 .mu.m or more in thickness, in which an insulating f |
| 7388238 |
Semiconductor integrated circuit device with reduced leakage current |
June 17, 2008 |
| The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconduct |
| 7387233 |
RFID card issuing system |
June 17, 2008 |
| In this REID card issuing system, manual operations are required only in two steps of: inputting personal information of an RFID card holder to register it in database; and pushing a shutter button of a camera when a photograph is being taken. Also, software controls are employed for the |
| 7386064 |
Communication semiconductor integrated circuit device and a wireless communication system |
June 10, 2008 |
| In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is |
| 7385870 |
Semiconductor memory device and semiconductor integrated circuit device |
June 10, 2008 |
| A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power contr |
| 7385869 |
Microcomputer and microprocessor having flash memory operable from single external power supply |
June 10, 2008 |
| A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit gen |
| 7385853 |
Data processing device |
June 10, 2008 |
| A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and |
| 7385838 |
Semiconductor device with a non-erasable memory and/or a nonvolatile memory |
June 10, 2008 |
| A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, there |
| 7385380 |
Switching power supply |
June 10, 2008 |
| In a switching power supply apparatus for performing a switching control of a power MOS transistor that flows current to a coil and converting input voltage into output voltage, even if there occurs offset voltage in a current sensing operational amplifier, source potential of a current |
| 7385279 |
Semiconductor device and a method of manufacturing the same |
June 10, 2008 |
| A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, |
| 7385278 |
Strobe light control circuit and IGBT device |
June 10, 2008 |
| As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit fo |
| 7384834 |
Semiconductor device and a method of manufacturing the same |
June 10, 2008 |
| A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the m |
| 7384820 |
Method of manufacturing a semiconductor device |
June 10, 2008 |
| A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all t |
| 7384582 |
Mold cleaning sheet and method for producing semiconductor devices using the same |
June 10, 2008 |
| A cleaning sheet (29) is formed with a trough-hole (29a) at a portion corresponding to a cavity of a mold along with a slit (29b) or a flow cavity cut (29c) at every corner at an outer periphery of the through-hole (29a) and is placed between a first mold half and a second mold half |
| 7383138 |
Semiconductor device |
June 3, 2008 |
| A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is |
| 7382681 |
Semiconductor integrated circuit |
June 3, 2008 |
| A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clo |
| 7382175 |
Frequency mixer preventing degradation in linearity on amplitude of input signal |
June 3, 2008 |
| A frequency mixer includes a first N channel MOS transistor, second and third N channel MOS transistors constituting a local oscillator signal differential pair, and having substantially identical properties, a first load, and a second load. The first N channel MOS transistor receives an |
| 7382160 |
Differential output circuit with reduced differential output variation |
June 3, 2008 |
| In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and |
| 7382045 |
IC card and method of manufacturing the same |
June 3, 2008 |
| An IC body is loaded to a case 2 made of thermosetting resin material and sealed with a sealing portion made of thermosetting resin material to be integrated, whereby an IC card is manufactured. The IC body comprises: a wiring substrate formed with an external connection terminal at a ba |
| 7382026 |
Semiconductor memory device and method of manufacturing the same |
June 3, 2008 |
| A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically con |
| 7380149 |
Information processing device |
May 27, 2008 |
| A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second ar |
| 7379521 |
Delay circuit with timing adjustment function |
May 27, 2008 |
| In a phase locked loop circuit, a phase comparator compares the phase of input clock and that of output clock, and provides a control signal as the comparison result. A charge pump circuit includes a clamp circuit, and based on the control signal, provides a control voltage of which |
| 7379366 |
Thin film magnetic memory device capable of conducting stable data read and write operations |
May 27, 2008 |
| A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed |
| 7379345 |
Nonvolatile semiconductor memory device that achieves speedup in read operation |
May 27, 2008 |
| A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset |
| 7379327 |
Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories |
May 27, 2008 |
| A method and system for providing a magnetic memory. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through |
| 7378887 |
Semiconductor integrated circuit with power-on state stabilization |
May 27, 2008 |
| The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermi |
| 7378706 |
Semiconductor device and method of manufacturing the same |
May 27, 2008 |
| An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate |
| 7378690 |
Method for forming patterns on a semiconductor device using a lift off technique |
May 27, 2008 |
| Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a r |
| 7378333 |
Semiconductor device and manufacturing method thereof |
May 27, 2008 |
| The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the p |
| 7377031 |
Fabrication method of semiconductor integrated circuit device |
May 27, 2008 |
| A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in |
| 7376819 |
Data processor with selectable word length |
May 20, 2008 |
| An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 bits or 32 bits, in |
| 7376783 |
Processor system using synchronous dynamic memory |
May 20, 2008 |
| A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic me |
| 7376190 |
Asynchronous data transmitting apparatus |
May 20, 2008 |
| An asynchronous data transmitting apparatus includes data signal transmission lines; two control transmission lines having a minimum delay and maximum delay respectively; a transmitter; and a receiver. The transmitter includes a data transmitting unit that transmits a data signal thr |
