| Patent Number |
Title Of Patent |
Date Issued |
| RE40139 |
Wafer having chamfered bend portions in the joint regions between the contour of the cut-away po |
March 4, 2008 |
| A wafer having chamfered bent portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer such as an orientation flatness. The chipping of the wafer can be prevented, and in coating the wafer with a photoresist, forming an epiaxially grown layer |
| RE39895 |
Semiconductor integrated circuit arrangement fabrication method |
October 23, 2007 |
| To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable sta |
| RE39645 |
Compressed image decompressing device |
May 22, 2007 |
| An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the |
| RE39579 |
Semiconductor integrated circuit device comprising RAM with command decode system and logic circ |
April 17, 2007 |
| A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control |
| RE39529 |
Graphic processing apparatus utilizing improved data transfer to reduce memory size |
March 27, 2007 |
| A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data |
| D504433 |
Memory card |
April 26, 2005 |
|
| 7421534 |
Data protection for non-volatile semiconductor memory using block protection flags |
September 2, 2008 |
| Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when |
| 7420838 |
Semiconductor device |
September 2, 2008 |
| To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an in |
| 7420834 |
Semiconductor integrated circuit device |
September 2, 2008 |
| The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in corres |
| 7420284 |
Semiconductor device and manufacturing method thereof |
September 2, 2008 |
| A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connec |
| 7420281 |
Stacked chip semiconductor device |
September 2, 2008 |
| A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an interface circuit |
| 7420278 |
Semiconductor device |
September 2, 2008 |
| The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing producti |
| 7419916 |
Manufacturing method of semiconductor device |
September 2, 2008 |
| The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenc |
| 7419902 |
Method of manufacture of semiconductor integrated circuit |
September 2, 2008 |
| In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes |
| 7419901 |
Semiconductor device and a method of manufacturing the same |
September 2, 2008 |
| In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing |
| 7419869 |
Semiconductor device and a method for manufacturing the same |
September 2, 2008 |
| Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate |
| 7418688 |
Routing analysis method, logic synthesis method and circuit partitioning method for integrated c |
August 26, 2008 |
| The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method compr |
| 7418602 |
Memory card |
August 26, 2008 |
| In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised |
| 7418250 |
Quadrature mixer circuits and mobile terminal using the same |
August 26, 2008 |
| Because there are different voltages at two current output terminals of a current divider, the voltages at the current input terminals of two current switch circuits are not affected mutually even with a large amplitude of local signals. Accordingly, the performance of a quadrature m |
| 7417838 |
Semiconductor integrated circuit |
August 26, 2008 |
| An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in th |
| 7417414 |
Semiconductor device provided with feedback circuit including resistive element and capacitive e |
August 26, 2008 |
| The present invention provides a switching power supply circuit capable of stabilizing an output voltage as well as increasing a response speed of the output voltage by improving a phase margin of an open loop as a whole of the switching power supply circuit. The switching power supply c |
| 7416970 |
Method for manufacturing semiconductor device |
August 26, 2008 |
| A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a s |
| 7416964 |
Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer |
August 26, 2008 |
| The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space |
| 7416133 |
IC card |
August 26, 2008 |
| An IC card is prevented from falling off readily an electronic device while maintaining the mechanical strength of the IC card. A recess for preventing a memory card from falling off an electronic device is provided at the side of one side of a principal surface of a cap of the memor |
| 7415576 |
Data processor with block transfer control |
August 19, 2008 |
| A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an e |
| 7415254 |
Power control circuit, semiconductor device and transceiver circuit using the same |
August 19, 2008 |
| There is provided a power control circuit having a stable high-speed operation, and a semiconductor device and a transceiver circuit using it. The power control circuit controls the gain of an amplifier so that power outputted from the amplifier reaches a desired value according to a |
| 7414912 |
Semiconductor flash memory |
August 19, 2008 |
| A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a pr |
| 7414909 |
Nonvolatile semiconductor memory |
August 19, 2008 |
| There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the mem |
| 7414821 |
Semiconductor integrated circuit device |
August 19, 2008 |
| Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input |
| 7414293 |
Structure and method of applying localized stresses to the channels of PFET and NFET transistors |
August 19, 2008 |
| A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region fo |
| 7414283 |
Semiconductor device |
August 19, 2008 |
| A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. T |
| 7413930 |
Lead frame and method of manufacturing the lead frame |
August 19, 2008 |
| A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead gr |
| 7412616 |
Semiconductor integrated circuit |
August 12, 2008 |
| A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface |
| 7412101 |
Semiconductor device and an image processor |
August 12, 2008 |
| An apparatus for encoding a plurality of image data series and decoding a plurality of encoded image data series includes an interface control circuit for executing data read/write operation from and to a memory area, an encoding/decoding circuit for selectively executing encoding of |
| 7411860 |
Multiport semiconductor memory device |
August 12, 2008 |
| In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD-Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access |
| 7411834 |
Nonvolatile semiconductor memory device |
August 12, 2008 |
| A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y di |
| 7411831 |
Disk processing apparatus with voltage generating circuit having a boost ratio control |
August 12, 2008 |
| The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a char |
| 7411805 |
Semiconductor integrated circuit device |
August 12, 2008 |
| A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the dela |
| 7411457 |
Power amplifying semiconductor integrated circuit device for use in communication equipment |
August 12, 2008 |
| The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in |
| 7411413 |
Pulse latch circuit and semiconductor integrated circuit |
August 12, 2008 |
| The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in wh |
| 7411365 |
Drive control device of motor and a method of start-up |
August 12, 2008 |
| A drive control device of motor capable of starting up even a motor of such a type that the polarity of induced voltage does not switch every 180.degree. of electrical angle or the polarity, positive or negative, does not occur with accuracy without causing a reverse rotation is prov |
| 7411302 |
Semiconductor device and a method of manufacturing the same and designing the same |
August 12, 2008 |
| There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near |
| 7411301 |
Semiconductor integrated circuit device |
August 12, 2008 |
| In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For examp |
| 7411267 |
Semiconductor integrated circuit device |
August 12, 2008 |
| The invention provides a semiconductor integrated circuit device with improved designing efficiency while achieving higher functions. An inner circuit is surrounded by a plurality of cells in which a first switch element for connecting a power supply voltage line or a ground voltage |
| 7411253 |
CMOS transistors using gate electrodes to increase channel mobilities by inducing localized chan |
August 12, 2008 |
| A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surfa |
| 7411242 |
Miniaturized virtual grounding nonvolatile semiconductor memory device and manufacturing method |
August 12, 2008 |
| The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yiel |
| 7411238 |
Semiconductor integrated circuit device and a method of manufacturing the same |
August 12, 2008 |
| In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as a lo |
| 7410834 |
Method of manufacturing a semiconductor device |
August 12, 2008 |
| A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surf |
| 7408818 |
Semiconductor device undergoing defect detection test |
August 5, 2008 |
| A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply |
| 7408405 |
High-frequency power amplifier module |
August 5, 2008 |
| For use in an amplifier configuration including a high-power amplifier and a low-power amplifier which are always interconnected in terms of high frequencies and between which switching is made using no switches, a highly stable high-frequency power amplifier module with high isolation |
