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Renesas Electronics Corporation Patents
Assignee:
Renesas Electronics Corporation
Address:
Kanagawa, JP
No. of patents:
2056
Patents:












Patent Number Title Of Patent Date Issued
RE43663 Semiconductor device September 18, 2012
In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the
RE43444 Semiconductor device having an improved connection arrangement between a semiconductor pellet an June 5, 2012
A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the
RE43443 Leadframe semiconductor integrated circuit device using the same, and method of and process for June 5, 2012
In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semico
RE43222 Semiconductor integrated circuit device March 6, 2012
A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second
RE42972 Semiconductor device having an improved connection arrangement between a semiconductor pellet an November 29, 2011
A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the
RE41721 Semiconductor device having an improved connected arrangement between a semiconductor pellet and September 21, 2010
A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the
RE41478 Semiconductor device having an improved connection arrangement between a semiconductor pellet an August 10, 2010
A semiconductor device comprising a semiconductor pellet mounted on a pellet mounting area of the main surface of a base substrate, in which first electrode pads arranged on the back of the base substrate are electrically connected to bonding pads arranged on the main surface of the
8589612 Computer system including an interrupt controller November 19, 2013
A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs;
8589606 Physical layer circuit November 19, 2013
Provided is a physical layer circuit. Upon detecting a connection recognition signal from an output of a differential input terminal, a first detection circuit outputs a first control signal for allowing an upper layer to output a power supply control signal for turning on a power su
8589108 Semiconductor device failure analysis method and apparatus and program November 19, 2013
A semiconductor device failure analysis method and apparatus and a computer program for the method and apparatus are provided. The method includes: an observation image acquisition process of acquiring a voltage contrast image by charging an exposed conductive layer of a semiconductor
8587995 Semiconductor device November 19, 2013
For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and
8587908 Semiconductor device November 19, 2013
It is desired to effectively suppress breaking of a protection target circuit caused by direct application of an ESD surge voltage to the circuit. The semiconductor device includes: a VDD pad; a signal output pad; a GND pad; a high-potential power source line; a signal line; a low-po
8587370 Semiconductor device reducing leakage current of transistor November 19, 2013
A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electr
8587282 Integrated circuit device for switching regulator having the same clock frequency as the switchi November 19, 2013
An integrated circuit device for a switching regulator, includes: a controller configured to generate a digital duty signal for a current mode control of the switching regulator based on an output voltage to be supplied from the switching regulator to a load circuit; and a switching
8587135 Semiconductor device having electrode/film opening edge spacing smaller than bonding pad/electro November 19, 2013
A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance bet
8587133 Semiconductor device November 19, 2013
An improved reliability of a junction region between a bonding wire and an electrode pad in an operation at higher temperature is presented. A semiconductor device includes a semiconductor chip provided on a lead frame, which are encapsulated with an encapsulating resin. Lead frames
8587087 Semiconductor device and manufacturing method of the same November 19, 2013
In order to improve characteristics of an IGBT, particularly, to reduce steady loss, turn-off time and turn-off loss, a thickness of a surface semiconductor layer is set to about 20 nm to 100 nm in an IGBT including: a base layer; a buried insulating film provided with an opening part; t
8587085 Semiconductor device with trench isolation having a diffusion preventing film and manufacturing November 19, 2013
There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive
8587027 Field effect transistor, method of manufacturing the same, and semiconductor device November 19, 2013
A J-FET includes a channel layer of a first conductivity type (a Si-doped n-type AlGaAs electron supply layers 3 and 7, undoped AlGaAs spacer layers 4 and 6, and an undoped InGaAs channel layer 5) formed above a semi-insulating GaAs substrate, an upper semiconductor layer made up of
8586992 Semiconductor device November 19, 2013
A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] c
8586478 Method of making a semiconductor device November 19, 2013
An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the
8586475 Semiconductor device including gate electrode for applying tensile stress to silicon substrate, November 19, 2013
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are impla
8586437 Semiconductor device and method of manufacturing the semiconductor device November 19, 2013
A method of manufacturing a semiconductor device includes forming a first region including a FinFET (Fin Field Effect Transistor), forming a second region including a PlanarFET (Planar Field Effect Transistor), forming first extension regions in the plurality of fins in the first region,
8586416 Method of manufacturing semiconductor device November 19, 2013
Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball
8583999 Display control apparatus November 12, 2013
A display control apparatus includes a comparison control unit which performs a cyclic redundancy check over an arbitrary region of image data. The comparison control unit includes a region control unit which selects a region of the image data based on comparison region information f
8582383 Semiconductor memory device with hidden refresh and method for controlling the same November 12, 2013
A semiconductor memory device includes a memory cell array having plural memory cells that require a refresh operation when retaining data; a read/write control unit that performs read-access or write-access of memory cell address specified for the memory cell array based on instruct
8582366 Semiconductor device using charge pump circuit November 12, 2013
A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit c
8581894 Output circuit, data driver and display device November 12, 2013
An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit. The third power supply voltage is intermediate between the first and second power supply voltages. The differential amplifier circuit includes, between the first and second po
8581566 Power supply controller having analog to digital converter November 12, 2013
A power supply control method of performing a feedback control of an output voltage based on a deviation signal for a standard voltage value serving as a target value for the output voltage and a digital signal generated by analog/digital (A/D) conversion of the output voltage, the m
8581415 Semiconductor device and a method of manufacturing the same November 12, 2013
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask,
8581410 Semiconductor device and method of manufacturing the same November 12, 2013
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring
8581395 Hybrid integrated circuit device and electronic device November 12, 2013
A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear su
8581368 Method for manufacturing semiconductor device, semiconductor chip, and semiconductor wafer November 12, 2013
A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting
8581350 Field effect transistor and semiconductor device, and method for manufacturing same November 12, 2013
Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode
8581340 Semiconductor device of which breakdown voltage is improved November 12, 2013
A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate through a gate insulating film; a source diffusion layer and a drain diffusion layer formed on both sides of the gate electrode, respectively, in the semiconductor subst
8581333 Semiconductor device and method for manufacturing the same November 12, 2013
A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected
8581328 Semiconductor memory device November 12, 2013
In a semiconductor memory device having split-gate MONOS memory cells, disturb resistance during writing by a SSI method is improved. In addition, with an improvement in the disturb resistance of a non-selected memory cell, a reduction in the area occupied by a memory module can be a
8581302 Semiconductor device including chip with complementary I/O cells November 12, 2013
Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O ce
8581299 Semiconductor device November 12, 2013
In a semiconductor device, at least one of the ratio (collector contact area/collector active area) in the High Side IGBT and the ratio (contact area on p.sup.+ region/p.sup.+ region area) is higher than the ratio in the Low Side IGBT. Thus, it is possible to develop without substantial
8580662 Manufacture method of a split gate nonvolatile memory cell November 12, 2013
A split gate nonvolatile memory cell is provided with a first diffusion region, a second diffusion region, and a channel region formed between the first and second diffusion regions, including a first channel region having a predetermined dopant concentration. The first channel region is
8580632 Semiconductor device and method of manufacturing same November 12, 2013
To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of
8580620 Method of manufacturing semiconductor device November 12, 2013
To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of
8578135 Apparatus for calculating and prefetching a branch target address November 5, 2013
A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing appar
8576643 Semiconductor integrated circuit November 5, 2013
A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize
8576634 Semiconductor device comprising a memory cell group having a gate width larger than a second mem November 5, 2013
The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile
8575987 Level shift circuit November 5, 2013
A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply ci
8575978 Semiconductor device, electronic device, and method of testing the semiconductor device November 5, 2013
A coupling failure of a supply terminal or a ground terminal is easily detected. A diode is disposed between a supply terminal of a semiconductor device and a first I/O terminal so that the supply terminal is located on a cathode side, and the first I/O terminal is located on an anod
8575969 Semiconductor device having differential pair transistors with a switchable tail current November 5, 2013
A semiconductor device configured that its differential pair is made operable in both states of high speed with a high consumption current and low speed with a low consumption current. A differential circuit includes differential pair transistors and a tail current source for supplying a
8575757 Semiconductor device and method of manufacturing the same November 5, 2013
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring s
8575733 Semiconductor device November 5, 2013
The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS.cndot.FET for a high side switch and a power MOS.cndot.FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the

 
 
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