| Patent Number |
Title Of Patent |
Date Issued |
| 7629915 |
High resolution time-to-digital converter and method thereof |
December 8, 2009 |
| A time-to-digital converter (TDC) is disclosed, the TDC comprising: a plurality of parallel circuits for receiving a common first clock and for generating a plurality of delayed clocks; a plurality of sampling circuits for receiving and sampling said delayed clocks at an edge of a se |
| 7626937 |
System and method for network connection detection |
December 1, 2009 |
| The present invention provides a system and method that operates in the link layer and detects connection status in a LAN. The system includes a request frame whose source address is an address of a node transmitting the request frame, a reply frame whose destination address is the sourc |
| 7623583 |
Apparatus and method for tracking a sampling clock of multi-carrier communication system |
November 24, 2009 |
| An apparatus and a method for tracking a sampling clock of a multi-carrier communication system are disclosed, the apparatus including a data removal module, a phase estimation module, and a sampling clock offset computation module. The data removal module is for generating a plurality |
| 7623520 |
Method and apparatus for routing packets |
November 24, 2009 |
| A method used for routing a data packet in a router having a first table used for recording a plurality of destination IP address and second table used for recording destination MAC address, wherein the plurality of destination IP address are different. The method includes: receiving a |
| 7623185 |
Synchronization control apparatus and method |
November 24, 2009 |
| A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and |
| 7622996 |
Multi-loop phase locked loop circuit |
November 24, 2009 |
| Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or t |
| 7622992 |
Power amplifier circuit having a bias signal inputted into input terminal and method thereof |
November 24, 2009 |
| The present invention discloses an adjustable gain power amplifier circuit. The adjustable gain power amplifier circuit includes a power amplifying unit for receiving and amplifying an input signal to generate an output signal; a power detecting unit for detecting power of the input |
| 7622956 |
Output driving circuit |
November 24, 2009 |
| Disclosed is an output driver, which comprises: a resistance element with resistance, coupled to an output terminal; a current mode driving circuit, coupled to the resistance element, for providing a first current to the output terminal, wherein at least one of the amount of the first |
| 7620381 |
Tri-state chopper for frequency conversion |
November 17, 2009 |
| A tri-state chopper (TSC) circuit and method is disclosed. The tri-state chopper (TSC) circuit receives an input signal and a ternary signal and generates an output signal, wherein: the output signal tracks the input signal in both magnitude and sign when the ternary signal is in a first |
| 7612645 |
Integrated inductor |
November 3, 2009 |
| An integrated inductor formed on a substrate comprises a metal layer pattern, a via layer pattern overlapping and electrically connected to the metal layer, and a redistribution layer pattern overlapping and electrically connected to the via layer. The metal layer pattern, the via la |
| 7612600 |
DC offset calibration apparatus and method |
November 3, 2009 |
| A DC offset calibration apparatus is disclosed. The DC offset calibration apparatus includes an adjustment circuit and an offset calibration circuit. The adjustment circuit is utilized for receiving an input signal and an offset calibration signal, and for adjusting the input signal to |
| 7610420 |
Data aggregation-distribution apparatus, date transmission system and method thereof |
October 27, 2009 |
| A data aggregation-distribution apparatus includes a plurality of port route units and a data processing unit. Every port route unit has a sending buffer and a receiving buffer. The data processing unit has a data aggregation unit and a data distribution unit. The data aggregation un |
| 7609041 |
Automatic voltage control circuit and method thereof |
October 27, 2009 |
| An automatic voltage control circuit controls a power supply unit to adjust a supply voltage provided by the power supply unit. The automatic voltage control circuit includes an oscillating unit, a frequency-comparing unit, and a control unit. The oscillating unit generates an oscill |
| 7605629 |
Adjusting circuit and method for delay circuit |
October 20, 2009 |
| Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating |
| 7600163 |
Convolutional interleaver and deinterleaver |
October 6, 2009 |
| An apparatus for receiving and storing an incoming sequence and for forwarding the bytes of the incoming sequence as an outgoing sequence in a different byte order includes a cache memory and a main memory for storing bytes of the incoming sequence until they can be forwarded as byte |
| 7600062 |
Method and apparatus for micro-code execution |
October 6, 2009 |
| A method for micro-code execution for an electronic device is disclosed. The method includes: providing the electronic device with a micro-code partitioned into a main core and at least a function code, the micro-code being stored in a first storage module of the electronic device; and w |
| 7600026 |
Apparatus and method for NAT/NAPT session management |
October 6, 2009 |
| The present invention provides an apparatus and method for NAT/NAPT session management used in a network switch controller. The apparatus comprises a translation table for storing related information of NAT/NAPT sessions, a register for storing setting values required by the apparatu |
| 7599010 |
TV receiver and analog TV signal processing method |
October 6, 2009 |
| The present invention provides a TV receiver and an analog TV signal processing method. The TV receiver includes a tuner, an analog-to-digital converter, and a digital filter module. The tuner is utilized to receive an RF signal and generate a first signal; the analog-to-digital converte |
| 7598798 |
Trimmer device and related trimming method |
October 6, 2009 |
| A trimmer device for adjusting a reference signal of a target circuit is disclosed. The trimmer device includes: a switch controlling module and an impedance adjustment circuit. The switch controlling module includes: a fuse, selectively being melted according to the reference signal; an |
| 7598789 |
Signal transferring system with unequal lengths of connecting paths and method thereof |
October 6, 2009 |
| The present invention relates to a signal transferring system. The signal transferring system includes a first and second layout paths, and a first and second circuits. Lengths of the first and second layout paths are different. The first and second circuits are used for transmitting and |
| 7583740 |
Apparatus and method for tracking sampling clock in multi-carrier communication system |
September 1, 2009 |
| An apparatus and method for tracking a sampling clock are disclosed. The apparatus includes a compensating circuit compensating phases of a first and a second received symbols according to a compensating signal and thereby generating a first and a second compensated symbols; a data r |
| 7583569 |
Apparatus and related method for generating a tracking error signal in an optical disc drive |
September 1, 2009 |
| The present invention discloses an apparatus for generating a tracking error signal in an optical disc drive. The disclosed apparatus includes: an analog-to-digital conversion module for receiving a plurality of analog signals generated by accessing an optical disc and for converting |
| 7583544 |
Data reading circuit |
September 1, 2009 |
| Disclosed is a data reading circuit, including: a first register, for receiving a first data signal and generating a second data signal by sampling the first data signal via the first edge of a first predetermined signal; a second register, for sampling a second data signal by the se |
| 7583324 |
Video data processing method and apparatus for processing video data |
September 1, 2009 |
| A video processing method utilized in a video data processing device for processing video data is disclosed. The video data includes at least a first video data set, and the video data processing device has a memory and a video decoder. The method includes utilizing the video decoder to |
| 7583323 |
Method and apparatus for scaling image block |
September 1, 2009 |
| An image scaling method for calculating a pixel value of a target pixel within a scaled image block is disclosed. The method includes selecting a plurality of reference pixels from the image block, wherein each reference pixel has a pixel value and corresponds to a transparency param |
| 7583213 |
Signal processing system capable of changing signal levels |
September 1, 2009 |
| A signal processing system for changing a level of an input signal to generate an output signal is disclosed. The signal processing system includes a shifter, a sigma-delta modulator, and a level adjuster. The shifter is utilized for receiving the input signal and for bit-shifting th |
| 7583166 |
Inductor Q factor enhancement apparatus has bias circuit that is coupled to negative resistance |
September 1, 2009 |
| The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative |
| 7583145 |
Hybrid output stage apparatus and related method thereof |
September 1, 2009 |
| The present invention discloses an apparatus for generating an output signal according to an input signal, including a signal generating circuit for generating a first and a second control signal according to the input signal; a first output stage has a first amplifying configuration |
| 7583124 |
Delaying stage selecting circuit and method thereof |
September 1, 2009 |
| A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sa |
| 7583117 |
Delay lock clock synthesizer and method thereof |
September 1, 2009 |
| A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock a |
| 7580044 |
Method and apparatus for non-linear dithering of images |
August 25, 2009 |
| A method for dithering an image is disclosed, which includes: storing a plurality of dithering parameters corresponding to a predetermined function for a predetermined input intensity range; and dithering pixels of the predetermined input intensity range according to the plurality of |
| 7579863 |
Circuit and method for reducing pin count of chip |
August 25, 2009 |
| A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to |
| 7577261 |
Wireless audio system using wireless local area network |
August 18, 2009 |
| A wireless audio system includes a first device and a second device. The first device includes a first logic and a first WLAN unit coupled to the first logic. The first logic performs audio processing to generate audio data. The first WLAN unit transmits the audio data through a radio |
| 7576618 |
Frequency synthesizer with a plurality of frequency locking circuits |
August 18, 2009 |
| The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a speci |
| 7567108 |
Apparatus and method for generating clock signal |
July 28, 2009 |
| The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; c |
| 7564927 |
Band averaging circuit and related method for carrier frequency offset estimation in a multi-ban |
July 21, 2009 |
| A band averaging circuit and a related method for estimating a carrier frequency offset are applied in a multi-band multi-carrier communication system. A packet of the multi-band multi-carrier communication system is transmitted via a plurality of carriers. The band averaging circuit |
| 7564320 |
Voltage-controlled oscillator |
July 21, 2009 |
| A voltage-controlled oscillator (VCO) includes: an oscillation unit, for generating an oscillation signal according to a biasing current; a current mirror, for providing the biasing current, the current mirror comprising: at least one first transistor, coupled between a first voltage |
| 7564306 |
Amplifier with common-mode feedback circuit |
July 21, 2009 |
| A common-mode feedback circuit is provided. An amplifier with a common-mode feedback circuit is compensated by adding a compensating unit so that the amplifier totally has two poles and one zero in its frequency response. Accordingly, the gain of the amplifier is not sacrificed, and |
| 7561980 |
Transmission medium testing apparatus and method |
July 14, 2009 |
| The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted signal which comprises |
| 7560991 |
Dynamically compensated operational amplifier |
July 14, 2009 |
| An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no ris |
| 7560990 |
Low noise amplifier and low noise amplifying method |
July 14, 2009 |
| A low noise amplifier for operating in response to different gain modes is disclosed. The low noise amplifier includes a voltage adjusting circuit, which provides a first bias voltage at a first gain mode and provides a second bias voltage at a second gain mode, where the second bias vol |
| 7558338 |
Method and apparatus for I/Q imbalance estimation |
July 7, 2009 |
| An apparatus and method for estimating an I/Q imbalance parameter of a receiver and a transmitter. An apparatus for estimating an I/Q imbalance parameter of a receiver, the apparatus comprising: a signal generator; a transmitter; a receiver; and an estimator. An apparatus for estimating |
| 7557740 |
Context-based adaptive binary arithmetic coding (CABAC) decoding apparatus and decoding method t |
July 7, 2009 |
| A decoding method is adapted to be implemented using a Context-based Adaptive Binary Arithmetic Coding (CABAC) decoding apparatus, and includes: initializing a plurality of context variables; storing the context variables; performing arithmetic decoding of a syntax element according |
| 7557638 |
Circuit for suppressing voltage jitter and method thereof |
July 7, 2009 |
| A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by util |
| 7554933 |
Echo cancellation device for full duplex communication systems |
June 30, 2009 |
| An echo cancellation apparatus of a transceiver in a full duplex communication system is disclosed. The full duplex communication system includes a transmitter section for transmitting a transmit signal and a receiver section for receiving a receive signal. The echo cancellation devi |
| 7554609 |
Method and apparatus for detecting and rejecting NTSC Interference in ATSC system |
June 30, 2009 |
| A method and apparatus for rejecting an interference signal from an input frequency spectrum. The method includes the steps of receiving the input signal; frequency-shifting the received input signal by a first frequency-shifting amount; and filtering the frequency-shifted input sign |
| 7551798 |
Apparatus for reducing zipper of image and method thereof |
June 23, 2009 |
| This invention is related to a method and an apparatus for reducing the zippers of image. The method uses a recovery model to reduce the zippers of image. The recovered model performs calculations which comprise the steps of setting a type of light sources and a sensing mode, measuring a |
| 7551696 |
Method and apparatus of detecting ISI/ICSI in an OFDM system |
June 23, 2009 |
| A method for detecting inter-symbol interference (ISI) in an OFDM system includes the steps of computing a first correlation value representing the correlation between a plurality of first signals of a first symbol and a plurality of second signals of a second symbol previous to the |
| 7551233 |
Image processing circuit having capability of reducing distorted/falsified phenomena of color co |
June 23, 2009 |
| An image processing circuit for processing a video signal includes: a separator for separating the video signal into a brightness signal and a color signal; a first filter coupled to the separator for filtering the color signal; and a second filter coupled to the separator for filtering |
| 7550958 |
Bandgap voltage generating circuit and relevant device using the same |
June 23, 2009 |
| A bandgap voltage generating circuit includes a circuit coupled to a first node and a second node, driving the first and the second nodes to the same voltage level. A first impedance element is coupled to the first node and a second impedance element is coupled to the second node, wh |
