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Rambus Inc. Patents
Rambus Inc.
Sunnyvale, CA
No. of patents:

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Patent Number Title Of Patent Date Issued
7370152 Memory controller with prefetching capability May 6, 2008
A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a p
7369444 Early read after write operation memory device, system and method May 6, 2008
A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address
7368961 Clock distribution network supporting low-power mode May 6, 2008
A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a
7366275 Output calibrator with dynamic precision April 29, 2008
An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver and adjusts the contr
7365581 Regulated adaptive-bandwidth PLL/DLL using self-biasing current from a VCO/VCDL April 29, 2008
A PLL/DLL circuit is current self-biased responsive to a current I.sub.ld provided from a voltage regulator to a VCO or VCDL. Bias current I.sub.bias, which is proportional to I.sub.ld, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an intercon
7363422 Configurable width buffered module April 22, 2008
A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer
7362800 Auto-configured equalizer April 22, 2008
An signal communication device having an auto-configured equalizer. The signal communication device includes a scoping circuit, buffer circuit, select circuit and equalizing circuit. A test signal is transmitted to the signal communication device via a signal path. The scoping circuit
7362626 Asynchronous, high-bandwidth memory component using calibrated timing elements April 22, 2008
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing
7362130 Method and device for transmission with reduced crosstalk April 22, 2008
The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrate
7360187 Mixed mode verifier April 15, 2008
A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropr
7360127 Method and apparatus for evaluating and optimizing a signaling system April 15, 2008
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a
7360050 Integrated circuit memory device having delayed write capability April 15, 2008
An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the
7356639 Configurable width buffered module having a bypass circuit April 8, 2008
A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one bypass circuit. A buffer device, such as a configurable width buffer device, is positioned between or with at least one
7353357 Apparatus and method for pipelined memory operations April 1, 2008
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semicond
7352234 Current control technique April 1, 2008
An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input
7349510 Apparatus for data recovery in a synchronous chip-to-chip system March 25, 2008
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The
7349484 Adjustable dual-band link March 25, 2008
A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a
7349279 Memory Device Having a Configurable Oscillator for Refresh Operation March 25, 2008
A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operati
7348811 Equalizing transceiver with reduced parasitic capacitance March 25, 2008
A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the
7346819 Through-core self-test with multiple loopbacks March 18, 2008
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the t
7337294 Method and apparatus for adjusting the performance of a synchronous memory system February 26, 2008
A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the
7336749 Statistical margin test methods and circuits February 26, 2008
Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique sample voltage, un
7331006 Multiple sweep point testing of circuit devices February 12, 2008
An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at
7330953 Memory system having delayed write timing February 12, 2008
A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory d
7330952 Integrated circuit memory device having delayed write timing based on read response time February 12, 2008
An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpir
7330951 Apparatus and method for pipelined memory operations February 12, 2008
A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle
7321524 Memory controller with staggered request signal output January 22, 2008
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock
7320082 Power control system for synchronous memory device January 15, 2008
A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the laten
7320047 System having a controller device, a buffer device and a plurality of memory devices January 15, 2008
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit
7319345 Wide-range multi-phase clock generator January 15, 2008
A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plu
7315929 Memory device January 1, 2008
A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a
7313639 Memory system and device with serialized data transfer December 25, 2007
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each
7308065 Delay locked loop circuitry for clock delay adjustment December 11, 2007
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second
7308058 Transparent multi-mode PAM interface December 11, 2007
Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the
7308048 System and method for selecting optimal data transition types for clock and data recovery December 11, 2007
A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as those associated with 2PAM and 4PAM signaling schemes. Select logic control circuitry
7308044 Technique for receiving differential multi-PAM signals December 11, 2007
A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an
7307560 Phase linearity test circuit December 11, 2007
A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plu
7307461 System and method for adaptive duty cycle optimization December 11, 2007
A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal
7302631 Low overhead coding techniques November 27, 2007
A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first
7301831 Memory systems with variable delays for write data signals November 27, 2007
Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also referred to as a wr
7298807 Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incomi November 20, 2007
A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present
7292637 Noise-tolerant signaling schemes supporting simplified timing and data recovery November 6, 2007
Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differen
7292629 Selectable-tap equalizer November 6, 2007
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time inter
7288973 Method and apparatus for fail-safe resynchronization with minimum latency October 30, 2007
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after
7287119 Integrated circuit memory device with delayed write command processing October 23, 2007
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense co
7287109 Method of controlling a memory device having a memory core October 23, 2007
Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sa
7285443 Stacked semiconductor module October 23, 2007
The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality
7280428 Multi-column addressing mode memory system including an integrated circuit memory device October 9, 2007
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a pag
7275171 Method and apparatus for programmable sampling clock edge selection September 25, 2007
A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower c
7274244 Pulse multiplexed output system September 25, 2007
A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a r
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