| Patent Number |
Title Of Patent |
Date Issued |
| RE39879 |
Method of transferring data by transmitting lower order and upper order memory address bits in s |
October 9, 2007 |
| A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of |
| RE39153 |
Connector with integral transmission line bus |
July 4, 2006 |
| A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative |
| RE38482 |
Delay stage circuitry for a ring oscillator |
March 30, 2004 |
| A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The |
| RE37452 |
At frequency phase shifting circuit for use in a quadrature clock generator |
November 20, 2001 |
| A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to |
| RE37409 |
Memory and method for sensing sub-groups of memory elements |
October 16, 2001 |
| A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory |
| RE36781 |
Differential comparator for amplifying small swing signals to a full swing output |
July 18, 2000 |
| A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output comp |
| RE36013 |
Differential charge pump circuit with high differential and low common mode impedance |
December 29, 1998 |
| A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative dif |
| 7627069 |
Digital transmit phase trimming |
December 1, 2009 |
| A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data |
| 7627066 |
Apparatus for data recovery in a synchronous chip-to-chip system |
December 1, 2009 |
| An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The |
| 7627043 |
Method and apparatus for transmitting data with reduced coupling noise |
December 1, 2009 |
| A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group o |
| 7627029 |
Margin test methods and circuits |
December 1, 2009 |
| Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some e |
| 7626880 |
Memory device having a read pipeline and a delay locked loop |
December 1, 2009 |
| A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an |
| 7626442 |
Low latency multi-level communication interface |
December 1, 2009 |
| A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a "symbol" at one of the valid voltage levels. In one |
| 7626248 |
Semiconductor package with a controlled impedance bus |
December 1, 2009 |
| An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to th |
| 7620116 |
Technique for determining an optimal transition-limiting code for use in a multi-level signaling |
November 17, 2009 |
| A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling |
| 7613883 |
Memory device with mode-selectable prefetch and clock-to-core timing |
November 3, 2009 |
| In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then output from the memory device via a signaling interface. A value that indicates a minimum numb |
| 7610447 |
Upgradable memory system with reconfigurable interconnect |
October 27, 2009 |
| Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets an |
| 7610417 |
Data-width translator coupled between variable-width and fixed-width data ports and supporting m |
October 27, 2009 |
| Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the inter |
| 7602209 |
Controlling memory devices that have on-die termination |
October 13, 2009 |
| A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circui |
| 7599422 |
Adjustable dual-band link |
October 6, 2009 |
| A communication system utilizing an adjustable link has at least a first data transmission circuit including at least a first communication link circuit. The first communication link circuit has a baseband circuit and at least a passband circuit. The baseband circuit corresponds to a |
| 7599390 |
Approximate bit-loading for data transmission over frequency-selective channels |
October 6, 2009 |
| A high-speed communications system utilizes approximate bit-loading during data transmission in a channel. In one embodiment, a plurality of parallel data preparation circuits in a data transmission circuit receive respective subsets of a data stream, each of the respective subsets of |
| 7599239 |
Methods and systems for reducing heat flux in memory systems |
October 6, 2009 |
| Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat |
| 7596175 |
Methods and circuits for performing margining tests in the presence of a decision feedback equal |
September 29, 2009 |
| Described are methods and circuits for margin testing receivers equipped with Decision Feedback Equalization (DFE) or other forms of feedback that employ historical data to reduce intersymbol interference (ISI). In one example, a high-speed serial receiver with DFE injects the correct |
| 7593470 |
High-speed communication system with a feedback synchronization loop |
September 22, 2009 |
| In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differentia |
| 7593271 |
Memory device including multiplexed inputs |
September 22, 2009 |
| Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be rece |
| 7592824 |
Method and apparatus for test and characterization of semiconductor components |
September 22, 2009 |
| A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing |
| 7590175 |
DFE margin test methods and circuits that decouple sample and feedback timing |
September 15, 2009 |
| Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some e |
| 7587012 |
Dual loop clock recovery circuit |
September 8, 2009 |
| A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase differen |
| 7581121 |
System for a memory device having a power down mode and method |
August 25, 2009 |
| A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exit |
| 7581078 |
Memory controller for non-homogeneous memory system |
August 25, 2009 |
| A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second |
| 7577789 |
Upgradable memory system with reconfigurable interconnect |
August 18, 2009 |
| Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filt |
| 7576573 |
Wave shaping output driver to adjust slew rate and/or pre-emphasis of an output signal |
August 18, 2009 |
| Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality o |
| 7574616 |
Memory device having a power down exit register |
August 11, 2009 |
| A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an ac |
| 7571330 |
System and module including a memory device having a power down mode |
August 4, 2009 |
| A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the me |
| 7570726 |
Master device with time domains for slave devices in synchronous memory system |
August 4, 2009 |
| A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave |
| 7565480 |
Dynamic memory supporting simultaneous refresh and data-access transactions |
July 21, 2009 |
| Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed |
| 7565479 |
Memory with refresh cycle donation to accommodate low-retention-storage rows |
July 21, 2009 |
| In a dynamic random access memory device, refreshing each normal-retention row of storage cells once per refresh interval, refreshing each low-retention row of storage cells more than once per refresh interval and refreshing each high-retention row of storage cells that is associated |
| 7565468 |
Integrated circuit memory device and signaling method for adjusting drive strength based on topo |
July 21, 2009 |
| An integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory |
| 7564258 |
Calibration methods and circuits to calibrate drive current and termination impedance |
July 21, 2009 |
| Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termi |
| 7562285 |
Unidirectional error code transfer for a bidirectional data link |
July 14, 2009 |
| A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data |
| 7562271 |
Memory system topologies including a buffer device and an integrated circuit memory device |
July 14, 2009 |
| Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be pro |
| 7558150 |
Memory controller with staggered request signal output |
July 7, 2009 |
| A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock |
| 7548601 |
Slave device with synchronous interface for use in synchronous memory system |
June 16, 2009 |
| A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave |
| 7546390 |
Integrated circuit device and signaling method with topographic dependent equalization coefficie |
June 9, 2009 |
| An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental m |
| 7543172 |
Strobe masking in a signaling system having multiple clock domains |
June 2, 2009 |
| Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components of a host system use th |
| 7542857 |
Technique for determining performance characteristics of electronic devices and systems |
June 2, 2009 |
| A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then mea |
| 7539882 |
Self-powered devices and methods |
May 26, 2009 |
| A system includes a computing device that selectively communicates with a self-powered device. The self-powered device has several modes of operation, including a first low-power mode of operation and a second high-power mode of operation. The self-powered device is to communicate wi |
| 7539802 |
Integrated circuit device and signaling method with phase control based on information in extern |
May 26, 2009 |
| An integrated circuit device includes a transmitting means for transmitting transmit data to an external signal line and a storing means for storing a first value representative of a transmit phase adjustment that is used to adjust when the transmit data is transmitted by the transmi |
| 7538424 |
System and method for dissipating heat from a semiconductor module |
May 26, 2009 |
| The system includes a circuit board, a semiconductor module, a heat dissipator, and at least one thermal via. The circuit board has substantially flat opposing first and second sides. The semiconductor module includes multiple semiconductor devices. The semiconductor module is orient |
| 7536494 |
Expandable slave device system with buffered subsystems |
May 19, 2009 |
| A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master |
