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Rambus Inc. Patents
Assignee:
Rambus Inc.
Address:
Sunnyvale, CA
No. of patents:
962
Patents:


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Patent Number Title Of Patent Date Issued
RE43720 Integrated circuit device having stacked dies and impedance balanced transmission lines October 9, 2012
A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated
RE42785 Semiconductor module with serial bus connection to multiple dies October 4, 2011
A semiconductor module is provided which includes a .[.beat.]. .Iadd.heat .Iaddend.spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electric
RE42429 Semiconductor module with serial bus connection to multiple dies June 7, 2011
A semiconductor module is provided which includes a .[.beat.]. .Iadd.heat .Iaddend.spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electric
RE42318 Semiconductor module with serial bus connection to multiple dies May 3, 2011
A semiconductor module is provided which includes a .[.beat.]. .Iadd.heat .Iaddend.spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electric
RE39879 Method of transferring data by transmitting lower order and upper order memory address bits in s October 9, 2007
A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of
RE39153 Connector with integral transmission line bus July 4, 2006
A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative
RE38482 Delay stage circuitry for a ring oscillator March 30, 2004
A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The
RE37452 At frequency phase shifting circuit for use in a quadrature clock generator November 20, 2001
A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to
RE37409 Memory and method for sensing sub-groups of memory elements October 16, 2001
A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory
RE36781 Differential comparator for amplifying small swing signals to a full swing output July 18, 2000
A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output comp
RE36013 Differential charge pump circuit with high differential and low common mode impedance December 29, 1998
A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative dif
8588349 Interference cancellation in variable codelength systems for multi-access communication November 19, 2013
A receiver employs low-rate processing to synthesize the effect of high-rate interference in a received multi-rate signal. Each high-rate subchannel is analyzed on its low-rate descendents to produce symbol estimates for each low-rate symbol interval. The symbol estimates are applied
8588280 Asymmetric communication on shared links November 19, 2013
Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the
8588012 Balanced on-die termination November 19, 2013
Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling
8583071 Methods and circuits for detecting and reporting high-energy particles using mobile phones and o November 12, 2013
Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or
8582391 Adjusting clock error across a circuit interface November 12, 2013
A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured fo
8581920 Utilizing masked data bits during accesses to a memory November 12, 2013
Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input t
8581755 Multiple word data bus inversion November 12, 2013
A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding wit
8571126 Multi-antenna transmitter for multi-tone signaling October 29, 2013
Embodiments of a communication circuit are described. This communication circuit includes an input node (212) to receive a set of data symbols and a partitioner (216) coupled to the input node. The partitioner is to divide the set of data symbols into M irregular subgroups of data sy
8564328 High speed signaling system with adaptive transmit pre-emphasis October 22, 2013
A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication o
8300745 Iterative interference cancellation using mixed feedback weights and stabilizing step sizes October 30, 2012
A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation
8300477 Piecewise erasure of flash memory October 30, 2012
Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-e
8296540 Method and apparatus for adjusting the performance of a synchronous memory system October 23, 2012
A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from
8295118 Self-timed interface for strobe-based systems October 23, 2012
A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction
8295107 Asynchronous pipelined memory access October 23, 2012
A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations.
8292445 Optical system for a light emitting diode with collection, conduction, phosphor directing, and o October 23, 2012
An optical system with an LED light source utilizes a base with an inverted conical shape to conduct light to a phosphor layer. The phosphor layer emits light from both upper and lower surfaces. The base and a substantially mirror image cap element facilitate efficient extraction of
8289032 Integrated circuit having receiver jitter tolerance ("JTOL") measurement October 16, 2012
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock sign
8286046 Integrated circuit testing module including signal shaping interface October 9, 2012
Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew ra
8281055 Memory systems and methods for dividing physical memory locations into temporal memory locations October 2, 2012
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the inter
8279976 Signaling with superimposed differential-mode and common-mode signals October 2, 2012
A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and seco
8279948 Interface with variable data rate October 2, 2012
A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage
8279094 Encoding and decoding techniques with improved timing margin October 2, 2012
Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second
8278968 Calibration methods and circuits to calibrate drive current and termination impedance October 2, 2012
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termi
8278964 Method and apparatus for test and characterization of semiconductor components October 2, 2012
A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing
8275030 Signaling system with selectively-inhibited adaptive equalization September 25, 2012
An integrated circuit having a receiver that selectively inhibits incoming data from being used to update adaptively generated controls. Sampling circuitry generates a plurality of samples of an incoming signal. Control circuitry generates an inhibit signal in either a first state or
8275027 Multi-mode transmitter September 25, 2012
A multi-mode transmitter within an integrated circuit device. The multi-mode transmitter transmits a first data sequence in a baseband signal when a first transmission mode is enabled, and transmits the first data sequence in a multi-band signal when a second transmission mode is ena
8271747 Mask key selection based on defined selection criteria September 18, 2012
An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that wil
8271745 Memory controller for non-homogeneous memory system September 18, 2012
A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second
8270501 Clocking architectures in high-speed signaling systems September 18, 2012
Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits
8264906 Adjusting clock error across a circuit interface September 11, 2012
A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured fo
8261039 Memory controllers, methods, and systems supporting multiple memory modes September 4, 2012
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of whi
8260979 Method and apparatus for simultaneous bidirectional signaling in a bus topology September 4, 2012
A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is pre
8256123 Displacement sensing using a flexible substrate September 4, 2012
Angular displacement of a flexible substrate is determined based on an electrical change of a mm-wave circuit associated with the flexible substrate. This electrical change may relate to, for example, one or more of a phase shift, an amplitude shift, a frequency shift, or a pulse shi
8255734 Multi-drop signaling system and method employing source termination August 28, 2012
A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition,
8248884 Method of controlling a memory device having multiple power modes August 21, 2012
A memory device includes a clock receiver, a command interface, and a data interface separate from the command interface. A memory controller provides the command interface with a command that specifies a write operation. After a programmable latency period transpires from providing
8243783 Adaptive equalization using correlation of edge samples with data patterns August 14, 2012
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while som
8243484 Adjustable width strobe interface August 14, 2012
A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data
8237484 Clock distribution circuit August 7, 2012
A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signal
8237468 Driver calibration methods and circuits August 7, 2012
Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with
8233567 Method and apparatus for data recovery July 31, 2012
A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data re
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