| Patent Number |
Title Of Patent |
Date Issued |
| 7622352 |
Multi-step gate structure and method for preparing the same |
November 24, 2009 |
| A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step |
| 7611949 |
Method of fabricating metal-oxide-semiconductor transistor |
November 3, 2009 |
| A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is |
| 7595467 |
Fault detection system and method for managing the same |
September 29, 2009 |
| A fault detection system comprises a data server configured to collect parameters incoming from at least one apparatus, at least one fault-sensing module configured to generate an alarm signal if the parameter exceeds a predetermined specification, a monitoring module configured to r |
| 7592219 |
Method of fabricating capacitor over bit line and bottom electrode thereof |
September 22, 2009 |
| A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then |
| 7582524 |
Method for preparing a memory structure |
September 1, 2009 |
| A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporatin |
| 7569909 |
Phase change memory devices and methods for manufacturing the same |
August 4, 2009 |
| Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A fir |
| 7569845 |
Phase-change memory and fabrication method thereof |
August 4, 2009 |
| A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the |
| 7569460 |
Capacitor structure and method for preparing the same |
August 4, 2009 |
| A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the elect |
| 7566895 |
Phase change memory device and method for fabricating the same |
July 28, 2009 |
| A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by one of the conduc |
| 7557407 |
Recessed gate structure and method for preparing the same |
July 7, 2009 |
| A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the |
| 7541241 |
Method for fabricating memory cell |
June 2, 2009 |
| A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two |
| 7541116 |
Mask at frequency domain and method for preparing the same and exposing system using the same |
June 2, 2009 |
| A mask at frequency domain comprises a plurality of amplitude patterns positioned on a first surface of the mask and a plurality of phase patterns positioned on a second surface of the mask. The amplitude patterns have different vertical thicknesses to change the amplitude of an expo |
| 7538043 |
Phase change memory device and fabrication method thereof |
May 26, 2009 |
| A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer |
| 7538018 |
Gate structure and method for fabricating the same, and method for fabricating memory and CMOS t |
May 26, 2009 |
| A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner co |
| 7535050 |
Memory structure with high coupling ratio |
May 19, 2009 |
| A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the |
| 7531438 |
Method of fabricating a recess channel transistor |
May 12, 2009 |
| A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An imp |
| 7524732 |
Semiconductor device with L-shaped spacer and method of manufacturing the same |
April 28, 2009 |
| A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring acti |
| 7521372 |
Method of fabrication of phase-change memory |
April 21, 2009 |
| A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor |
| 7511333 |
Nonvolatile memory cell with multiple floating gates and a connection region in the channel |
March 31, 2009 |
| A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same condu |
| 7510955 |
Method of fabricating multi-fin field effect transistor |
March 31, 2009 |
| A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to |
| 7494865 |
Fabrication method of metal oxide semiconductor transistor |
February 24, 2009 |
| A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the p |
| 7485917 |
Split gate flash memory cell and fabrication method thereof |
February 3, 2009 |
| A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, |
| 7479452 |
Method of forming contact plugs |
January 20, 2009 |
| A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly |
| 7462545 |
Semicondutor device and manufacturing method thereof |
December 9, 2008 |
| A semiconductor device is provided. The semiconductor device has a gate structure, a source region, a drain region, and a pair of dielectric barrier layers. The gate structure is formed on a substrate. The source region and the drain region are formed in the substrate next to the gate |
| 7459383 |
Fabricating method of gate structure |
December 2, 2008 |
| A gate structure comprising a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer is provided. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate die |
| 7436526 |
Real-time system for monitoring and controlling film uniformity and method of applying the same |
October 14, 2008 |
| A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer s |
| 7435645 |
Dynamic random access memory (DRAM) |
October 14, 2008 |
| A dynamic random access memory (DRAM) includes a substrate, an active device and a deep trench capacitor. A trench and a deep trench are formed in the substrate. The active device is disposed on the substrate. The active device includes a gate structure and a doped region. The gate s |
| 7435643 |
Fabrication method of a dynamic random access memory |
October 14, 2008 |
| A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the |
| 7427569 |
Metal etching process and rework method thereof |
September 23, 2008 |
| A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask |
| 7419872 |
Method for preparing a trench capacitor structure |
September 2, 2008 |
| A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a |
| 7407886 |
Method for preparing a contact plug structure |
August 5, 2008 |
| A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged |
| 7402364 |
Semiconductor device with loop line pattern structure, method and alternating phase shift mask f |
July 22, 2008 |
| An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180.degree. phase difference from second regions with 0.degr |
| 7394124 |
Dynamic random access memory device |
July 1, 2008 |
| A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the su |
| 7387942 |
Substrate isolation in integrated circuits |
June 17, 2008 |
| Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the |
| 7383095 |
Integration system and the method for operating the same |
June 3, 2008 |
| An integration system for obtaining a set of overlay offset parameters of a first process layer which is going to be formed in an assigned photolithography tool with an assigned mask and an assigned pre-tool. By using the integration system, the set of overlay offset parameters of the |
| 7375027 |
Method of providing contact via to a surface |
May 20, 2008 |
| A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To prote |
| 7362428 |
Highly sensitive defect detection method |
April 22, 2008 |
| A highly sensitive defect detection method is disclosed. A medium with a refractive index greater than 1 is formed on a sample. As a result, incident light projected by a defect detecting system attenuates less when reaching the bottom defects. The detection sensitivity of the defect |
| 7358149 |
Substrate isolation in integrated circuits |
April 15, 2008 |
| Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric (520) faces the |
| 7354837 |
Fabrication method for single and dual gate spacers on a semiconductor device |
April 8, 2008 |
| A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the |
| 7349289 |
Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM |
March 25, 2008 |
| A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the la |
| 7348622 |
Memories having a charge storage node at least partially located in a trench in a semiconductor |
March 25, 2008 |
| A memory charge storage node (120.1, 120.2, 120.3) is at least partially located in a trench (124). The memory comprises a transistor including a source/drain region (170) present at a first side (124.1) but not a second side (124.2) of the trench. Before forming conductive material |
| 7344995 |
Method for preparing a structure with high aspect ratio |
March 18, 2008 |
| The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concav |
| 7336340 |
Method of exposure error adjustment in photolithography for multiple products |
February 26, 2008 |
| A method of adjusting exposure error for multiple products is described. First, one Photo Feed Back System (PFBS) suited to host-product or miscellaneous product is chosen. Different standard points and compensation difference for host-product or miscellaneous product are provided. T |
| 7332396 |
Semiconductor device with recessed trench and method of fabricating the same |
February 19, 2008 |
| A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and e |
| 7332387 |
MOSFET structure and method of fabricating the same |
February 19, 2008 |
| A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced by the bird's beak |
| 7329550 |
Method for analyzing the structure of deep trench capacitors and a preparation method thereof |
February 12, 2008 |
| A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspection area, of the die ar |
| 7326992 |
Nonvolatile memory cell with multiple floating gates formed after the select gate |
February 5, 2008 |
| In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrat |
| 7323729 |
Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing pre |
January 29, 2008 |
| A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and |
| 7320912 |
Trench capacitors with buried isolation layer formed by an oxidation process and methods for man |
January 22, 2008 |
| A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in areas surrounding a lower |
| 7319058 |
Fabrication method of a non-volatile memory |
January 15, 2008 |
| A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a |
