| Patent Number |
Title Of Patent |
Date Issued |
| 6399432 |
Process to control poly silicon profiles in a dual doped poly silicon process |
June 4, 2002 |
| For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amor |
| 6317804 |
Concurrent serial interconnect for integrating functional blocks in an integrated circuit device |
November 13, 2001 |
| A circuit arrangement and method interface multiple functional blocks within an integrated circuit device via a concurrent serial interconnect capable of routing separate serial command, data and clock signals between functional blocks in the device. The concurrent serial interconnect |
| 6304988 |
Scan testable circuit arrangement |
October 16, 2001 |
| A circuit arrangement utilizes a common bus for functional operations of logic circuits and for scan testing the logic circuits. In one embodiment, input/output ports and scan test ports of the logic circuits are switchably coupled to a bus. For functionally testing the logic circuits, |
| 6275680 |
Hardware PCH checking for personal handyphone system portable station |
August 14, 2001 |
| A circuit arrangement on a handset for checking paging information transmitted in a personal handyphone system. The circuit arrangement includes a memory portion for storing the identification numbers of the handset and the cell station from which the handset receives calls, and an i |
| 6261939 |
Pad metallization over active circuitry |
July 17, 2001 |
| Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry a |
| 6260092 |
Point to point or ring connectable bus bridge and an interface with method for enhancing link pe |
July 10, 2001 |
| A point-to-point or ring connectable bus bridge replicates a PCI bus serially over a point-to-point or ring connected network and the Fiber Channel interface enhanced by a method for improving link performance provides the serial connection. Participants can appear as resources or ma |
| 6258204 |
Electrically planar upper electrode cover |
July 10, 2001 |
| The present invention comprises the electrode assemblies themselves as well as improved plasma plate. The plasma side of the plate is counter bored in the area of the gas inlet holes to an appropriate depth. On the opposite side of the plate, another set of bores are placed around the ou |
| 6251747 |
Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
June 26, 2001 |
| A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during proc |
| 6247095 |
Digital reverberation processor and method for generating digital reverberation |
June 12, 2001 |
| A reverberation processor and method for generating reverberation in a digital audio processing system. The reverberation processor uses register files programmed with tap page and tap offset addresses to gather the audio data for the reverberation taps. The address of each block tra |
| 6246107 |
Semiconductor device arrangement having configuration via adjacent bond pad coding |
June 12, 2001 |
| According to an example embodiment, the present invention is directed to a configurable semiconductor device wherein the placement of bond wires and bonding pads are assembled to bond internal configuration pads at the die level. One aspect of the invention is a multiple-configuration |
| 6235557 |
Programmable fuse and method therefor |
May 22, 2001 |
| A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. In an example embodiment, a fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existin |
| 6228757 |
Process for forming metal interconnects with reduced or eliminated metal recess in vias |
May 8, 2001 |
| A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The process includes forming a via in a device layer of the semiconductor |
| 6228707 |
Semiconductor arrangement having capacitive structure and manufacture thereof |
May 8, 2001 |
| A semiconductor manufacturing process is used to develop capacitors in compact areas such as at or near the interconnect level. According to one example embodiment, a substrate having a first and second conductor is separated by a dielectric, once the dielectric is removed a trench is |
| 6226736 |
Microprocessor configuration arrangement for selecting an external bus width |
May 1, 2001 |
| A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the |
| 6225662 |
Semiconductor structure with heavily doped buried breakdown region |
May 1, 2001 |
| A semiconductor structure with a heavily doped buried breakdown region and a method for manufacture. A source region is disposed in a substrate and is doped with dopant of a type opposite that of the substrate. A drain region is disposed in the substrate at the surface and doped with dop |
| 6222353 |
Voltage regulator circuit |
April 24, 2001 |
| The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory t |
| 6221735 |
Method for eliminating stress induced dislocations in CMOS devices |
April 24, 2001 |
| The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a m |
| 6215879 |
Method for introducing harmonics into an audio stream for improving three dimensional audio posi |
April 10, 2001 |
| Method for introducing harmonics into an audio stream for improving three dimensional audio positioning. The method adds high frequency harmonics into sampled sound signals to replace high frequency sound components eliminated before sampling. By adding high frequency harmonics into the |
| 6202183 |
Analog test access port and method therefor |
March 13, 2001 |
| An improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC is described wherein the testability is independent of the core logic of that IC, which does not require the dedication of any pin solely to the testing of that IC. A uniform analog |
| 6202152 |
System and method for accessing information decrypted in multiple-byte blocks |
March 13, 2001 |
| A system and method for accelerating information transfers from an encrypted memory to a requesting device in a system utilizing a decryption engine is provided. The decryption engine fetches and decrypts a first information block having a greater byte count than the number of bytes of |
| 6177697 |
Arrangement for DRAM cell using shallow trench isolation |
January 23, 2001 |
| A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a ca |
| 6154803 |
Method and arrangement for passing data between a reference chip and an external bus |
November 28, 2000 |
| A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement |
| 6140188 |
Semiconductor device having load device with trench isolation region and fabrication thereof |
October 31, 2000 |
| A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up |
