| Patent Number |
Title Of Patent |
Date Issued |
| 5895961 |
Semiconductor device with a planarized interconnect with poly-plug and self-aligned contacts |
April 20, 1999 |
| A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is co |
| 5656861 |
Self-aligning contact and interconnect structure |
August 12, 1997 |
| An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insula |
| 5620919 |
Methods for fabricating integrated circuits including openings to transistor regions |
April 15, 1997 |
| An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from sh |
| 5557575 |
Look ahead flag for FIFO |
September 17, 1996 |
| The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output because the required calculations are |
| 5493530 |
Ram with pre-input register logic |
February 20, 1996 |
| A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. |
| 5483104 |
Self-aligning contact and interconnect structure |
January 9, 1996 |
| An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insula |
| 5477074 |
Semiconductor structure using local planarization with self-aligned transistors |
December 19, 1995 |
| A CMOS integrated circuit uses self-aligned transistors combined with local planarization in the vicinity of the transistors so as allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, |
| 5384744 |
Look ahead flag for FIFO |
January 24, 1995 |
| The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output because the required calculations are |
| 5365104 |
Oxynitride fuse protective/passivation film for integrated circuit having resistors |
November 15, 1994 |
| An oxynitride passivation layer and/or fuse protective layer for an SRAM cell having load resistors, where the composition of the oxynitride layer minimizes the effect of hydrogen diffusion on the resistance of underlying load resistors. The index of refraction of the oxynitride is betwe |
| 5359226 |
Static memory with self aligned contacts and split word lines |
October 25, 1994 |
| A compact static random access memory is formed using both split word lines and self aligned contacts. Self aligned contacts between gates of the pull-down transistor and cross-couple interconnects decreases the critical spacing between elements of the cell and permit the cell to be smal |
| 5348897 |
Transistor fabrication methods using overlapping masks |
September 20, 1994 |
| Transistor fabrication methods are provided which are suitable, for example, for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment in which |
| 5340774 |
Semiconductor fabrication technique using local planarization with self-aligned transistors |
August 23, 1994 |
| A CMOS integrated circuit fabrication technique for forming self-aligned transistors combined with local planarization in the vicinity of the transistors so as to allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible |
| 5172211 |
High resistance Polysilicon load resistor |
December 15, 1992 |
| A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each |
| 5168076 |
Method of fabricating a high resistance polysilicon load resistor |
December 1, 1992 |
| A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each |
| 5166771 |
Self-aligning contact and interconnect structure |
November 24, 1992 |
| An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from sh |
| 5124774 |
Compact SRAM cell layout |
June 23, 1992 |
| A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate |
