| Patent Number |
Title Of Patent |
Date Issued |
| RE39501 |
Multiple network protocol encoder/decoder and data processor |
March 6, 2007 |
| A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol la |
| D515086 |
Housing for a scalable graphics processor |
February 14, 2006 |
|
| 7454566 |
System and method for adaptive RAID configuration |
November 18, 2008 |
| One embodiment of the present invention includes the steps of determining the optimal RAID level to implement for a given disk drive array, and to the extent applicable, making unallocated disk space available to the user in the form of unprotected disk space. The method efficiently |
| 7454320 |
System and method for calculating partial differential equations in a hardware graphics pipeline |
November 18, 2008 |
| A system and method are provided for computing partial differential equations in a hardware graphics pipeline. Initially, input is received in a hardware graphics pipeline. Next, the input is processed to generate a solution to a partial differential equation utilizing the hardware g |
| 7453158 |
Pad over active circuit system and method with meshed support structure |
November 18, 2008 |
| An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incur |
| 7451259 |
Method and apparatus for providing peer-to-peer data transfer within a computing environment |
November 11, 2008 |
| A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity |
| 7450136 |
Apparatus and system for generating texture derivatives for pixel processing |
November 11, 2008 |
| A pixel processing unit reduces the number of pixels exterior to a primitive that must be rendered solely for the purpose of generating texture derivative information required to shade pixels within the primitive. In one embodiment, the alignment of group footprints is selected to re |
| 7450129 |
Compression of streams of rendering commands |
November 11, 2008 |
| A distributed rendering system with compression of streams of rendering commands. The controlling device 110 fits streams of rendering commands to the rendering devices 120 within the frame duration by distributing compressed streams. Streams are compressed by caching relatively dupl |
| 7450123 |
System and method for render-to-texture depth peeling |
November 11, 2008 |
| A system, method and computer program product are provided for performing depth peeling. In use, a first rendering pass is executed for collecting information relating to a first depth layer. Further, at least one additional rendering pass is executed for collecting additional inform |
| 7450120 |
Apparatus, system, and method for Z-culling |
November 11, 2008 |
| A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics pr |
| 7450027 |
Method and system for implementing a serial enclosure management interface for a computer system |
November 11, 2008 |
| A method and system for implementing a serial enclosure management interface is disclosed. In one embodiment, the LED indicators for a storage device in an external enclosure are managed. First, a set of bit patterns for driving the LED indicators is repeatedly placed on a serial bus |
| 7447873 |
Multithreaded SIMD parallel processor with loading of groups of threads |
November 4, 2008 |
| In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to be processed received as a stream of input data blocks, and the input data blocks are load |
| 7447490 |
In-situ gain calibration of radio frequency devices using thermal noise |
November 4, 2008 |
| An apparatus for calibrating gain of an radio frequency receiver ("Rx") is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its o |
| 7446780 |
Temporal antialiasing in a multisampling graphics pipeline |
November 4, 2008 |
| Multisampling techniques provide temporal as well as spatial antialiasing. Coverage for a primitive is be determined at multiple sample locations for a pixel. In one embodiment, coverage is determined using boundary equations representing a boundary surface of the primitive in a thre |
| 7446773 |
Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler |
November 4, 2008 |
| An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or more different types of processors. The scheduler schedules operations on the different |
| 7444551 |
Method and apparatus for system status monitoring, testing and restoration |
October 28, 2008 |
| Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failu |
| 7444491 |
Automatic resource sharing between FIFOs |
October 28, 2008 |
| Embodiments of the present invention recite a method and system for allocating memory resources. In one embodiment, a control component coupled with a memory device determines that a data buffer adjacent to a boundary of a first FIFO queue does not contain current data. The control c |
| 7443389 |
Pixel clock spread spectrum modulation |
October 28, 2008 |
| Circuits, methods, and apparatus that reduce the peak or maximum EMI generated by video signals provided to a CRT or digital display monitor. One exemplary embodiment provides for spreading the spectrum of the video signal in order to spread or diffuse its peak spectral component. This |
| 7441137 |
Voltage regulator with internal controls for adjusting output based on feed-forward load informa |
October 21, 2008 |
| Methods and apparatus for controlling a voltage supplied to a device based on an anticipated change in load current demanded by the device are provided. In response to detecting the anticipated change in load current, a load control signal may be generated that causes the voltage reg |
| 7441087 |
System, apparatus and method for issuing predictions from an inventory to access a memory |
October 21, 2008 |
| A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset o |
| 7439988 |
Apparatus, system, and method for clipping graphics primitives with respect to a clipping plane |
October 21, 2008 |
| Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical represen |
| 7439979 |
Shader with cache memory |
October 21, 2008 |
| A shader having a cache memory for storing program instructions is described. The cache memory beneficially stores both current programming instructions for a fragment program being run and "look-ahead" programming instructions. The cache memory supports a scheduler that forms progra |
| 7439883 |
Bitstream generation for VLC encoded data |
October 21, 2008 |
| A bitstream generator is described, for placing variable length coding (VLC) data into a fixed width data stream. The bitstream generator includes an input for receiving VLC data; the VLC data may be separated into a value component, and a length component. The bitstream generator al |
| 7437548 |
Network level protocol negotiation and operation |
October 14, 2008 |
| Method and apparatus for network level protocol negotiation for Internet Protocol Security (IPSec) and Internet Protocol Payload Compression (IPComp) are described. More particularly, IPSec and IPComp capabilities are instantiated in a network processor unit of a network interface in at |
| 7434032 |
Tracking register usage during multithreaded processing using a scoreboard having separate memor |
October 7, 2008 |
| A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction bu |
| 7433981 |
System and method for using co-processor hardware to accelerate highly repetitive actions |
October 7, 2008 |
| An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related methods for power and computationally efficiency in performing repetitive tasks. The system |
| 7433909 |
Processing architecture for a reconfigurable arithmetic node |
October 7, 2008 |
| A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functional |
| 7433398 |
Equalization for DMT and OFDM communication systems |
October 7, 2008 |
| The invention provides a DMT or OFDM equalization system that deals with each tone not only separately, but also globally, which provides better overall performance. In the inventive system, only M+T variables are required to be determined, where M is the number of tones and T repres |
| 7432981 |
Apparatus, system, and method for processing digital audio/video signals |
October 7, 2008 |
| Apparatus, system, and method for processing digital audio/video signals are described. In one embodiment, a decoder is configured to process an input signal having an analog television format. The decoder includes a signal detector, and the signal detector is configured to determine |
| 7429528 |
Method of fabricating a pad over active circuit I.C. with meshed support structure |
September 30, 2008 |
| An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incur |
| 7428566 |
Multipurpose functional unit with multiply-add and format conversion pipeline |
September 23, 2008 |
| A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations. |
| 7426724 |
Optimized chaining of vertex and fragment programs |
September 16, 2008 |
| A system optimizes two or more stream processing programs based upon the data exchanged between the stream processing programs. The system alternately processes each stream processing program to identify and remove dead program code, thereby improving execution performance. Dead prog |
| 7426597 |
Apparatus, system, and method for bus link width optimization of a graphics system |
September 16, 2008 |
| A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negot |
| 7426594 |
Apparatus, system, and method for arbitrating between memory requests |
September 16, 2008 |
| Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory request generator is |
| 7425966 |
Pixel center position displacement |
September 16, 2008 |
| A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within |
| 7425956 |
System and method for occlusion testing with deferred rendering |
September 16, 2008 |
| One embodiment of the present invention sets forth a method for implementing occlusion testing prior to processing a primitive command. The method includes the steps of determining that an occlusion test should be performed on an enclosed primitive, saving the primitive command on a |
| 7423882 |
Rotating clip |
September 9, 2008 |
| Apparatus and methods for mounting of a cooling device coupled to a circuit board include use of a clip that is rotated to mate with and engage the cooling device. Rotation of the clip occurs during installation of the cooling device and slides slots in the clip into interconnection |
| 7421604 |
Advanced voltage regulation using feed-forward load information |
September 2, 2008 |
| Methods and apparatus for controlling a voltage supplied to a device based on an anticipated change in load current demanded by the device are provided. In response to detecting the anticipated change in load current, a load control signal may be generated that causes the voltage reg |
| 7421303 |
Parallel LCP solver and system incorporating same |
September 2, 2008 |
| A Linear Complementarity Problem (LCP) solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time. |
| 7420931 |
Using TCP/IP offload to accelerate packet filtering |
September 2, 2008 |
| A method and apparatus for filtering a packet on a connection within a computing system. In one embodiment, the method includes: receiving the packet; delegating the packet to an offload unit for filtering the packet; and determining, by the offload unit, whether the connection is a |
| 7420572 |
Apparatus, system, and method for clipping graphics primitives with accelerated context switchin |
September 2, 2008 |
| An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to issue an initial set of outputs based on execution of a set of clipping operations. The graphics processing |
| 7420568 |
System and method for packing data in different formats in a tiled graphics memory |
September 2, 2008 |
| A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize |
| 7420565 |
Point-to-point bus bridging without a bridge controller |
September 2, 2008 |
| A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card. A first bus connection communicates data from the computer system to the integrated graphics subsystem. With a loopback card in |
| 7420557 |
Vertex processing when w=0 |
September 2, 2008 |
| Vertices defining a graphics primitive may be processed in homogeneous space and projected into normalized device coordinate space by dividing each coordinate of a vertex by w. When the w coordinate for a vertex is equal to zero, the projected coordinates are set equal to the homogeneous |
| 7418606 |
High quality and high performance three-dimensional graphics architecture for portable handheld |
August 26, 2008 |
| A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be processed using " |
| 7418576 |
Prioritized issuing of operation dedicated execution unit tagged instructions from multiple diff |
August 26, 2008 |
| A graphics processor buffers vertex thread and pixel threads. The different types of threads issue instructions corresponding to different sets of operations. A plurality of different types of execution units are provided, each type of execution unit servicing a different class of op |
| 7418537 |
Deadlock avoidance in a bus fabric |
August 26, 2008 |
| Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on |
| 7417637 |
Fairly arbitrating between clients |
August 26, 2008 |
| An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provides a signal to th |
| 7415575 |
Shared cache with client-specific replacement policy |
August 19, 2008 |
| A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results fro |
| 7414550 |
Methods and systems for sample rate conversion and sample clock synchronization |
August 19, 2008 |
| The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples created or mixed using any of the standard audio frequencies in the set H={8, 11.025, 22.05, |
