| Patent Number |
Title Of Patent |
Date Issued |
| 7354840 |
Method for opto-electronic integration on a SOI substrate |
April 8, 2008 |
| According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried ox |
| 7339254 |
SOI substrate for integration of opto-electronics with SiGe BiCMOS |
March 4, 2008 |
| According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed in the silicon la |
| 7338848 |
Method for opto-electronic integration on a SOI substrate and related structure |
March 4, 2008 |
| According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried ox |
| 7335547 |
Method for effective BiCMOS process integration |
February 26, 2008 |
| According to an exemplary embodiment, a method for integrating bipolar and CMOS devices on a substrate, where the substrate includes bipolar and CMOS regions and has a sacrificial oxide layer situated thereon, includes removing a portion of the sacrificial oxide layer in the bipolar regi |
| 7297992 |
Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process |
November 20, 2007 |
| According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further incl |
| 7291898 |
Selective and non-selective epitaxy for base integration in a BiCMOS process and related structu |
November 6, 2007 |
| According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer |
| 7291536 |
Fabricating a self-aligned bipolar transistor having increased manufacturability |
November 6, 2007 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer |
| 7282418 |
Method for fabricating a self-aligned bipolar transistor without spacers |
October 16, 2007 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a se |
| 7268038 |
Method for fabricating a MIM capacitor having increased capacitance density and related structur |
September 11, 2007 |
| According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of |
| 7235861 |
NPN transistor having reduced extrinsic base resistance and improved manufacturability |
June 26, 2007 |
| A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a |
| 7220639 |
Method for fabricating a MIM capacitor high-K dielectric for increased capacitance density and r |
May 22, 2007 |
| According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlN.sub.X (aluminum nitride) on the |
| 7217613 |
Low cost fabrication of high resistivity resistors |
May 15, 2007 |
| In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over the transistor gate |
| 7183627 |
Independent control of polycrystalline silicon-germanium in an HBT and related structure |
February 27, 2007 |
| In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH.sub.4. The polycrystalline silicon-germanium region can be, for example, a base contact in a |
| 7173318 |
On-chip inductors |
February 6, 2007 |
| Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is su |
| 7154161 |
Composite ground shield for passive components in a semiconductor die |
December 26, 2006 |
| According to one exemplary embodiment, a structure situated in a semiconductor die comprises an active shield situated in a substrate, where the active shield comprises a salicide layer situated on an active region, and where the active shield has a first conductivity type. The activ |
| 7132700 |
SiGe layer having small poly grains |
November 7, 2006 |
| A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. co |
| 7109125 |
Selective fabrication of high capacitance density areas in a low dielectric constant material |
September 19, 2006 |
| Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is |
| 7078744 |
Transistor emitter having alternating undoped and doped layers |
July 18, 2006 |
| A disclosed embodiment is a method for fabricating an emitter structure, comprising a step of conformally depositing an undoped polysilicon layer in an emitter window opening and over a base. Next, a doped polysilicon layer is non-conformally deposited over the undoped layer. Thereafter, |
| 7078310 |
Method for fabricating a high density composite MIM capacitor with flexible routing in semicondu |
July 18, 2006 |
| According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further |
| 7064415 |
Self-aligned bipolar transistor having increased manufacturability |
June 20, 2006 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer |
| 7064361 |
NPN transistor having reduced extrinsic base resistance and improved manufacturability |
June 20, 2006 |
| According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction |
| 7064073 |
Technique for reducing contaminants in fabrication of semiconductor wafers |
June 20, 2006 |
| According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, |
| 7063988 |
Circuit for detecting arcing in an etch tool during wafer processing |
June 20, 2006 |
| According to one exemplary embodiment, a circuit configured to interface with an etch tool comprises an ESC input for receiving a first signal from the etch tool, where the first signal indicates a magnitude of a chuck current passing through a chuck holding a wafer in the etch tool. |
| 7056822 |
Method of fabricating an interconnect structure employing air gaps between metal lines and betwe |
June 6, 2006 |
| An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first |
| 7052966 |
Deep N wells in triple well structures and method for fabricating same |
May 30, 2006 |
| A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N |
| 7049246 |
Method for selective fabrication of high capacitance density areas in a low dielectric constant |
May 23, 2006 |
| Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion |
| 7041569 |
Method for fabricating a high density composite MIM capacitor with reduced voltage dependence in |
May 9, 2006 |
| According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated wi |
| 7041564 |
Method for fabricating a self-aligned bipolar transistor |
May 9, 2006 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transistor also comprises a |
| 7033898 |
Method for fabricating a self-aligned bipolar transistor having recessed spacers |
April 25, 2006 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post |
| 7015115 |
Method for forming deep trench isolation and related structure |
March 21, 2006 |
| According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a |
| 6995449 |
Deep trench isolation region with reduced-size cavities in overlying field oxide |
February 7, 2006 |
| According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and |
| 6995068 |
Double-implant high performance varactor and method for manufacturing same |
February 7, 2006 |
| A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and tuning range. A s |
| 6992338 |
CMOS transistor spacers formed in a BiCMOS process |
January 31, 2006 |
| According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited over the substrate |
| 6984577 |
Damascene interconnect structure and fabrication method having air gaps between metal lines and |
January 10, 2006 |
| A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing |
| 6979626 |
Method for fabricating a self-aligned bipolar transistor having increased manufacturability and |
December 27, 2005 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer |
| 6972442 |
Efficiently fabricated bipolar transistor |
December 6, 2005 |
| One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the first wafer is transferre |
| 6965132 |
Polycrystalline silicon emitter having an accurately controlled critical dimension |
November 15, 2005 |
| According to a disclosed embodiment, an etch stop layer is fabricated on top of a base. An amorphous layer is then formed on top of the etch stop layer. An opening is then etched in the amorphous layer and the etch stop layer. The opening is etched with an opening width substantially equ |
| 6943414 |
Method for fabricating a metal resistor in an IC chip and related structure |
September 13, 2005 |
| According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprise |
| 6933202 |
Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure |
August 23, 2005 |
| According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming |
| 6933085 |
Transparent phase shift mask for fabrication of small feature sizes |
August 23, 2005 |
| In one exemplary embodiment, a resolution enhancement phase shift mask comprises a transparent substrate having a first clear region, a second clear region and a third clear region. An opaque film, such as chrome, is situated over at least a portion of the transparent substrate to define |
| 6927957 |
Electrostatic discharge clamp |
August 9, 2005 |
| According to one exemplary embodiment, an ESD bus clamp in an integrated circuit comprises an inverter having an input and an output. The ESD bus clamp further comprises a bipolar transistor having a base, an emitter, and a collector, where the base is connected to the output of the |
| 6924196 |
Anti-reflective coating and process using an anti-reflective coating |
August 2, 2005 |
| An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalli |
| 6919272 |
Method for patterning densely packed metal segments in a semiconductor die and related structure |
July 19, 2005 |
| A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etc |
| 6894328 |
Self-aligned bipolar transistor having recessed spacers and method for fabricating same |
May 17, 2005 |
| According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further includes a sacrificial post situa |
| 6893931 |
Reducing extrinsic base resistance in an NPN transistor |
May 17, 2005 |
| A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a ca |
| 6885056 |
High-k dielectric stack in a MIM capacitor and method for its fabrication |
April 26, 2005 |
| According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprise |
| 6867477 |
High gain bipolar transistor |
March 15, 2005 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor might be a lateral PNP bipolar transistor and the base may comprise, for example, N type single crystal silicon. The bipolar transistor further comprises an emitter |
| 6867440 |
Self-aligned bipolar transistor without spacers and method for fabricating same |
March 15, 2005 |
| According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated on a first and a se |
| 6861308 |
Method for fabrication of SiGe layer having small poly grains and related structure |
March 1, 2005 |
| A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, |
| 6838352 |
Damascene trench capacitor for mixed-signal/RF IC applications |
January 4, 2005 |
| A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first mater |
