| Patent Number |
Title Of Patent |
Date Issued |
| 7437354 |
Architecture for network search engines with fixed latency, high capacity, and high throughput |
October 14, 2008 |
| An improved architecture for a network search engine (NSE) is disclosed herein as including an interface manager, one or more levels of a splitting engine, an array of data processing units (DPUs), and a cascade block. A method for using the improved NSE architecture to form an effic |
| 7436688 |
Priority encoder circuit and method |
October 14, 2008 |
| A priority encoder circuit can include a number of sectional encoder circuits that each encode "m" inputs signals into sets of "P" encoder outputs, where m>p. Each sectional encoder circuit can also output a group indication signal representing the activation of any of the receive |
| 7436229 |
Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback inte |
October 14, 2008 |
| A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator ci |
| 7433217 |
Content addressable memory cell configurable between multiple modes and method therefor |
October 7, 2008 |
| A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one c |
| 7432750 |
Methods and apparatus for frequency synthesis with feedback interpolation |
October 7, 2008 |
| A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator ci |
| 7426518 |
System and method for efficiently searching a forwarding database that is split into a bounded n |
September 16, 2008 |
| A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub |
| 7417881 |
Low power content addressable memory |
August 26, 2008 |
| A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare l |
| 7412561 |
Transposing of bits in input data to form a comparand within a content addressable memory |
August 12, 2008 |
| An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one o |
| 7403407 |
Magnitude comparator circuit for content addressable memory with programmable priority selection |
July 22, 2008 |
| A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values. |
| 7401180 |
Content addressable memory (CAM) device having selectable access and method therefor |
July 15, 2008 |
| According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular s |
| 7392349 |
Table management within a policy-based routing system |
June 24, 2008 |
| A method of controlling a content addressable memory (CAM) device. A data structure is generated that specifies (i) a prioritized set of rules and (ii) storage locations within the CAM device for one or more match clauses of each of the rules. A new rule having a specified priority is |
| 7391200 |
P-channel power chip |
June 24, 2008 |
| An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N |
| 7389377 |
Access control list processor |
June 17, 2008 |
| An integrated circuit device for processing an access control list. The integrated circuit device includes a first content addressable memory (CAM) including a plurality of CAM blocks to generate respective match indices, each match index indicating a storage location within the corr |
| 7382637 |
Block-writable content addressable memory device |
June 3, 2008 |
| A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plu |
| 7379352 |
Random access memory (RAM) method of operation and device for search engine systems |
May 27, 2008 |
| A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) ma |
| 7366830 |
Row expansion reduction by inversion for range representation in ternary content addressable mem |
April 29, 2008 |
| A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key i |
| 7362602 |
Sense amplifier circuit and method |
April 22, 2008 |
| A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supply voltage and the |
| 7349332 |
Apparatus for queuing different traffic types |
March 25, 2008 |
| A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows |
| 7346000 |
Method and apparatus for throttling selected traffic flows |
March 18, 2008 |
| A traffic management processor that selectively throttles individual traffic flows or particular traffic types specified in a throttle control instruction, which may also cause the traffic management processor to throttle all network traffic. |
| 7342886 |
Method and apparatus for managing individual traffic flows |
March 11, 2008 |
| A traffic management processor for managing a number of traffic flows each including one or more packets includes a content address memory (CAM) device having a plurality of rows, each row storing a flow identification (ID) for a corresponding packet, the flow ID indicating to which traf |
| 7339810 |
Device and method for ensuring current consumption in search engine system |
March 4, 2008 |
| A search engine system (100) can include a key multiplexer (104) and logic circuit (108). A key from a previous operation can be received by logic circuit (108) and altered to generate an idle key. In a non-search operation, the idle key can be applied to a CAM section to draw current |
| 7337267 |
Hierarchical, programmable-priority content addressable memory system |
February 26, 2008 |
| A hierarchical programmable-priority content addressable memory (CAM) system including first, second and third CAM devices. The first CAM device has a first priority number output and a first enable input. The second CAM device has a priority number input and an enable output coupled |
| 7325091 |
Disabling defective blocks in a partitioned CAM device |
January 29, 2008 |
| A CAM device having a plurality of CAM blocks includes circuitry to disable one or more defective CAM blocks, and to selectively translate address space in the disabled CAM blocks to the remaining enabled CAM blocks. In one embodiment, each CAM block is coupled to a corresponding blo |
| 7324362 |
Content addressable memory cell configurable between multiple modes and method therefor |
January 29, 2008 |
| A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one c |
| 7323916 |
Methods and apparatus for generating multiple clocks using feedback interpolation |
January 29, 2008 |
| A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator ci |
| 7319602 |
Content addressable memory with twisted data lines |
January 15, 2008 |
| A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first da |
| 7317628 |
Memory device and sense amplifier circuit with faster sensing speed and improved insensitivities |
January 8, 2008 |
| A sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations (i.e., eliminated functional failures) is provided herein. According to one embodiment, the sense amplifier circuit associated with a row of memory cells within a memory |
| 7307861 |
Content addressable memory (CAM) cell bit line architecture |
December 11, 2007 |
| A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each mem |
| 7304873 |
Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor |
December 4, 2007 |
| A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value |
| 7298635 |
Content addressable memory (CAM) cell with single ended write multiplexing |
November 20, 2007 |
| A content addressable memory (CAM) cell circuit can include a match section that enables an impedance path coupled to a match line in response to a comparison between a data value and a compare data value. At least a first storage circuit can be connected to the match section, and pr |
| 7289442 |
Method and apparatus for terminating selected traffic flows |
October 30, 2007 |
| A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plurality of rows, each |
| 7283380 |
Content addressable memory with selective error logging |
October 16, 2007 |
| A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an e |
| 7281085 |
Method and device for virtualization of multiple data sets on same associative memory |
October 9, 2007 |
| A system (200) can provide data aggregation with a single primary table (206) formed in a content addressable memory (CAM) section (202). Within a primary table (206) CAM entries can be part of a primary table, one or more aggregate tables, or both. In one arrangement, valid bits in each |
| 7277983 |
Method and apparatus for smoothing current transients in a content addressable memory (CAM) devi |
October 2, 2007 |
| A CAM device (100) according to an embodiment can include a control circuit (106) that can sequentially activate, with dummy operations, an increasingly larger number of CAM blocks (102-1 to 102-16) in response to a start-up circuit (104) indication until an initial number of CAM blocks |
| 7277309 |
Interlocking memory/logic cell layout and method of manufacture |
October 2, 2007 |
| A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. M |
| 7277307 |
Column defect detection in a content addressable memory |
October 2, 2007 |
| A content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of columns of CAM cells, a plurality of storage elements, each for storing a column pass/fail signal indicating whether a corresponding column of CAM cells is designated |
| 7272684 |
Range compare circuit for search engine |
September 18, 2007 |
| A range matching circuit (100) may include a range compare circuit (102) that receives a first range value from a first value store (104) and a second range value from a second range store (106). A range compare circuit (102) can determine if a comparand value falls within a range de |
| 7272027 |
Priority circuit for content addressable memory |
September 18, 2007 |
| A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each |
| 7257763 |
Content addressable memory with error signaling |
August 14, 2007 |
| A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives |
| 7257084 |
Rollover bits for packet departure time calculator |
August 14, 2007 |
| A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for |
| 7254748 |
Error correcting content addressable memory |
August 7, 2007 |
| A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those |
| 7251707 |
Content based content addressable memory block enabling using search key |
July 31, 2007 |
| A content addressable memory includes a plurality of CAM blocks, each including an array of CAM cells to store a predetermined range of data values, a parsing circuit having an input to receive the search key and having an output to provide a selected portion of the search key in res |
| 7251147 |
Content comparator memory (CCM) device and method of operation |
July 31, 2007 |
| A content comparator memory (CCM) device can include a row (100) of CCM cells (102-1 to 102-I). Each CCM cell (102-1 to 102-I) can have a controllable signal path (104-1 to 104-I) arranged in series to form a match path (106) that provides a match indication MATCH that can be activat |
| 7246198 |
Content addressable memory with programmable word width and programmable priority |
July 17, 2007 |
| A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The |
| 7237156 |
Content addressable memory with error detection |
June 26, 2007 |
| A content addressable memory (CAM) device having concurrent compare and error checking capability. The content addressable memory (CAM) device includes circuitry to compare a comparand with a plurality of data words stored within the CAM device in a compare operation, and circuitry to |
| 7237058 |
Input data selection for content addressable memory |
June 26, 2007 |
| A method and apparatus for input data selection for content addressable memory. In one embodiment, the apparatus includes an array of CAM cells, a select circuit adapted to generate a plurality of select signals each indicative of a segment of input data provided to the CAM apparatus, an |
| 7230841 |
Content addressable memory having dynamic match resolution |
June 12, 2007 |
| A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in e |
| 7230840 |
Content addressable memory with configurable class-based storage partition |
June 12, 2007 |
| A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input |
| 7228378 |
Entry location in a content addressable memory |
June 5, 2007 |
| A method for performing a search in a content addressable memory ("CAM") device comprising comparing a search key with compound entries in a CAM array, wherein at least one of the compound entries includes (i) a ternary CAM word having a data word and a mask word, and (ii) a mask spe |
| 7221575 |
Pseudo ternary content addressable memory device having row redundancy and method therefor |
May 22, 2007 |
| A pseudo ternary content addressable memory (PTCAM) device (100) can include a number of PTCAM blocks (102-0 to 102-63), each of which can include a number of standard PTCAM rows (106-0 to 106-63) and a standard memory row (104-0 to 104-63) for storing and providing mask information |
