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NetLogic Microsystems, Inc. Patents
Assignee:
NetLogic Microsystems, Inc.
Address:
Mountain View, CA
No. of patents:
355
Patents:


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Patent Number Title Of Patent Date Issued
RE41351 CAM arrays having CAM cells therein with match line and low match line connections and methods o May 25, 2010
A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used
RE40932 Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations u October 6, 2009
A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including eithe
8589658 Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memo November 19, 2013
Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual
8589405 Token stitcher for a content search system having pipelined engines November 19, 2013
A content search system includes multiple pipelined search engines that implement different portions of a regular expression search operation. For some embodiments, the search pipeline includes a DFA engine, an NFA engine, and a token stitcher that combines partial match results gene
8582338 Ternary content addressable memory cell having single transistor pull-down stack November 12, 2013
Ternary CAM cells are disclosed that include a compare circuit that includes a discharge path having a single pull-down transistor coupled between the match line and ground potential.
8577921 Method and apparatus for enhanced hashing November 5, 2013
A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be
8572106 Memory management in a token stitcher for a content search system having pipelined engines October 29, 2013
A content search system includes multiple pipelined search engines that implement different portions of a regular expression search operation. For some embodiments, the search pipeline includes a DFA engine, an NFA engine, and a token stitcher that combines partial match results gene
8566533 System, method, and computer program product for conditionally sending a request for data to a n October 22, 2013
In operation, a first request for data is sent to a cache of a first node. Additionally, it is determined whether the first request can be satisfied within the first node, where the determining includes at least one of determining a type of the first request and determining a state of
8285974 Age matrix for queue entries dispatch order October 9, 2012
An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators asso
8274265 Multi-phase power system with redundancy September 25, 2012
An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and
8266373 Content addressable memory (CAM) device and method for updating data by multiplexing between key September 11, 2012
A content addressable memory (CAM) can include a CAM memory array having both a data field and a mask field. A multiplexer (MUX) can selectively load data from either a register or an external data input to one or both fields of the CAM memory array.
8248159 Model based distortion reduction for power amplifiers August 21, 2012
A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a fe
8230167 Block mapping circuit and method for memory device July 24, 2012
A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at lea
8229119 Secure modulation and demodulation July 24, 2012
A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signa
8214305 Pattern matching system and method for data streams, including deep packet inspection July 3, 2012
A data stream search system can include a plurality of search data inputs logically divided into at least M+N sets. The sets have a logical order with respect to one another, each set providing more than one bit value. A key application circuit can comprise a plurality of data paths that
8196017 Method for on-the-fly error correction in a content addressable memory(CAM) and device therefor June 5, 2012
A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value
8185689 Processor with compare operations based on any of multiple compare data segments May 22, 2012
A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit segment value forming different ones of the M search key segments according to a database
8176298 Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline May 8, 2012
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupl
8155236 Methods and apparatus for clock and data recovery using transmission lines April 10, 2012
A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is
8149862 Multi-protocol communication circuit April 3, 2012
A multi-protocol communication circuit, for example, a serializer-deserializer (SerDes) circuit for communicating between an internal logic circuit and an external link includes a select terminal configured to accept a select signal representing a plurality of mode select signal. A S
8122189 Methods for logically combining range representation values in a content addressable memory February 21, 2012
A method may include comparing a first content addressable memory ("CAM") entry with a first key value to generate a first comparison result; comparing each of multiple second CAM entries with a second key value to generate multiple second comparison results; and generating a match s
8111533 System for dynamically managing power consumption in a search engine February 7, 2012
The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active
8102936 Methods and apparatus for clock and data recovery using transmission lines January 24, 2012
A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is
8089794 Precharge circuits and methods for content addressable memory (CAM) and related devices January 3, 2012
A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value
8089793 Dynamic random access memory based content addressable storage element with concurrent read and January 3, 2012
A content addressable memory (CAM) cell includes a first storage element for storing a data value, a second storage element for storing the data value, and a compare circuit having first inputs to receive from the first storage element a first complementary data signal indicative of the
8086641 Integrated search engine devices that utilize SPM-linked bit maps to reduce handle memory duplic December 27, 2011
An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a search path of the
8085568 Methods and circuits for placing unused content addressable memory (CAM) cells into low current December 27, 2011
A method of placing a content addressable memory (CAM) into a low current state is disclosed. The CAM can include at least one storage location that does not store valid data for a compare operation and includes a plurality of CAM cells, each CAM cell having at least two data control
8082416 Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memo December 20, 2011
Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual
8073856 System and method for efficiently searching a forwarding database that is split into a bounded n December 6, 2011
A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub
8065456 Delegating network processor operations to star topology serial bus interfaces November 22, 2011
An advanced processor comprises a plurality of multithreaded processor cores configured to support a plurality of software generated read or write instructions for interfacing with a star topology serial bus interface. The multiple-core processor has at least one of an internal fast
8064510 Analog encoder based slicer November 22, 2011
A method and an apparatus for slicing an analog signal using an analog encoder.
8063811 Systems, circuits, and methods for pipelined folding and interpolating ADC architecture November 22, 2011
A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation uni
8059439 Encoding data for storage in a content addressable memory November 15, 2011
An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in each CAM
8054873 Joint phased training of equalizer and echo canceller November 8, 2011
A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC) is described. In one embodiment, which both the AEQ and AEC process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the
8054696 System and method to improve reliability in memory word line November 8, 2011
A method and apparatus are disclosed for improving reliability in a memory circuit. The method includes coupling a pull-down element to a word line, the pull-down element coupled distal to a word line driver. The method further includes, when the word line exhibits a defect causing a
8051085 Determining regular expression match lengths November 1, 2011
A method and apparatus are disclosed for determining the lengths of one or more substrings of an input string that matches a regular expression (regex) The input string is searched for the regex using an non-deterministic finite automaton (NFA), and upon detecting a match state a sel
8041757 Low power and low complexity adaptive self-linearization October 18, 2011
A method of signal processing comprises receiving an unknown input signal that includes a distorted component and an undistorted component, the unknown input signal having a sampling rate of R; and performing self-linearization based at least in part on the unknown signal to obtain a
8040943 Least mean square (LMS) engine for multilevel signal October 18, 2011
A method and an apparatus for slicing a multilevel analog signal using a two-level slicer having one threshold level to generate an analog error signal. The method may be performed by delaying a received multilevel analog signal in a plurality of serial analog stages (n), further del
8037224 Delegating network processor operations to star topology serial bus interfaces October 11, 2011
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupl
8032336 Distortion cancellation using adaptive linearization October 4, 2011
A method of signal processing includes receiving a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal, and performing linearization, based at least in part on the distorted s
8031503 System for dynamically managing power consumption in a search engine October 4, 2011
The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active
8031501 Segmented content addressable memory device having pipelined compare operations October 4, 2011
Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matchin
8023301 Content addressable memory device having state information processing circuitry September 20, 2011
Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner.
8023300 Content addressable memory device capable of parallel state information transfers September 20, 2011
Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a parallel manner.
8023299 Content addressable memory device having spin torque transfer memory cells September 20, 2011
A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell, a second MTJ element
8023298 Encoding data for storage in a content addressable memory September 20, 2011
Approaches for an improved encoding scheme that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded data word in
8018751 Ternary content addressable memory (TCAM) cells with low signal line numbers September 13, 2011
A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No
8015567 Advanced processor with mechanism for packet distribution at high line rate September 6, 2011
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupl
8000412 Low power serial link August 16, 2011
The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and
7995596 System and method for offloading packet protocol encapsulation from software August 9, 2011
A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.
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