| Patent Number |
Title Of Patent |
Date Issued |
| 7423414 |
Apparatus and method for switching regulator with compensation delay for output voltage error co |
September 9, 2008 |
| A hysteretic regulator is provided. The hysteretic regulator includes a delay compensation circuit that adds a delay to the output of the hysteretic comparator. The delay is dependent on the input voltage. For low duty cycles, the slope of the inductor current is much greater for the |
| 7423337 |
Integrated circuit device package having a support coating for improved reliability during tempe |
September 9, 2008 |
| An apparatus and method for increasing integrated circuit device package reliability is disclosed. According to one embodiment of the present invention, a support coating is added to a wafer after solder bumps have been added but prior to dicing. This support coating or underfill layer |
| 7422952 |
Method of forming a BJT with ESD self protection |
September 9, 2008 |
| A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting |
| 7422366 |
Current mirror methodology quantifying time dependent thermal instability accurately in SOI BJT |
September 9, 2008 |
| A current mirror method is provided that can be utilized to evaluate thermal issues is silicon-on-insulator (SOI) bipolar junction transistors (BJTs). The method significantly improves safe operating area (SOA) measurement sensitivity. Unlike conventional methods, the current mirror |
| 7420280 |
Reduced stress under bump metallization structure |
September 2, 2008 |
| An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer |
| 7419863 |
Fabrication of semiconductor structure in which complementary field-effect transistors each have |
September 2, 2008 |
| Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of its source/drain zones. Semiconductor dopant, typically a |
| 7419855 |
Apparatus and method for miniature semiconductor packages |
September 2, 2008 |
| A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor ch |
| 7417687 |
Video synchronization signal removal circuitry |
August 26, 2008 |
| A video synchronization signal removal circuit in which a synchronization signal component of an incoming video signal is detected whereupon a reference signal corresponding to a black video level is substituted substantially during the synchronization signal interval. |
| 7413927 |
Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip- |
August 19, 2008 |
| An apparatus and method for enhancing the formation of fillets around the periphery of assembled wafer-level chip scale packages when mounted onto substrates. The method includes fabricating a plurality of integrated circuit die on a first surface of a semiconductor wafer, each of the |
| 7412695 |
Transient state nodes and a method for their identification |
August 12, 2008 |
| Sequential digital integrated circuits have stable state nodes that are capable of retaining their state (logic value) even in the absence of any input directly driving these points. However, in addition to stable state nodes, some custom-designed digital circuits have so-called transien |
| 7411251 |
Self protecting NLDMOS, DMOS and extended voltage NMOS devices |
August 12, 2008 |
| In an NLDMOS, DMOS or NMOS active device the ability to withstand snapback under stress conditions is provided by moving the hot spot away from the drain contact region. This is achieved by moving the drain contact region further away from the gate and including an additional n-region ne |
| 7410879 |
System and method for providing a dual via architecture for thin film resistors |
August 12, 2008 |
| A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are forme |
| 7410813 |
Method of parallel lapping a semiconductor die |
August 12, 2008 |
| In a lapping process for lapping away layers from a semiconductor device, where the region of interest is located near an edge or corner of the device, the method includes adding additional semiconductor material adjacent the region of interest. |
| 7408400 |
System and method for providing a low voltage bandgap reference circuit |
August 5, 2008 |
| A system and method are disclosed for providing a low voltage bandgap reference circuit that provides a substantially constant output voltage over a range of values of temperature. For example, the bandgap reference circuit could be capable of providing output voltages that are as low as |
| 7408335 |
Low power, low noise band-gap circuit using second order curvature correction |
August 5, 2008 |
| A band-gap reference circuit comprising a first current source for generating a first reference current and a first circuit branch for receiving part of the first reference current. The first circuit branch comprises a first resistor having a positive temperature coefficient in serie |
| 7406101 |
System and method for providing on-chip delay measurements in serializer / deserializer systems |
July 29, 2008 |
| A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transmit data path of th |
| 7405100 |
Packaging of a semiconductor device with a non-opaque cover |
July 29, 2008 |
| Packages of semiconductor devices with non-opaque covers and methods for making the packages. The invention allows an encapsulant to be used with a non-opaque cover. By ensuring the cover is attached to a die in such a way as to expose bonding pads while sealing in the imaging portion of |
| 7404090 |
Device and computer system for power management using serial link connections |
July 22, 2008 |
| Power management for a computer system and device is accomplished by implementing two separate power modes in a serially-connected device, and selecting from the two power modes depending on the state of a receiver in the device. A signal detector within the receiver is connected to a |
| 7403749 |
Method and system for integrated circuit RF immunity enhancement |
July 22, 2008 |
| Method and system for enhancing RF immunity of integrated circuits (ICs). Susceptibility of different subcircuits within the IC is determined by simulation or bench testing. Relatively simple filters are implemented based on the susceptible frequency range and circuit parameters such as |
| 7403233 |
Video circuitry for controlling signal gain and reference black level |
July 22, 2008 |
| A multi-channel video signal processing circuit with a bias control and respective video channel gain controls. The bias signal, which corresponds to a nominal video signal brightness level, is shared among the video channels which, in accordance with respective video gain control si |
| 7403052 |
Power-on detect by measuring thermal voltage |
July 22, 2008 |
| A power-on detection circuit is arranged to cooperate with a thermal-voltage generator to determine when predictable circuit operation is achieved. The power-on detection circuit includes a comparator circuit and an inverter circuit. A power-on reset (POR) signal is generated by the |
| 7402984 |
Oscillation sensor for linear regulation circuit |
July 22, 2008 |
| An oscillation sensor for a regulator that provides dynamic control of a connection/disconnection of a compensation capacitance. The compensation capacitor is disconnected under normal operation and is automatically connected if oscillation is detected in the output and regulator's error |
| 7400187 |
Low voltage, low Z, band-gap reference |
July 15, 2008 |
| The present invention relates to a low impedance band-gap voltage reference circuit which comprises a band-gap reference circuit, a buffer circuit to reduce the impedance and related noise associated with band-gap references electronically coupled with the band-gap voltage reference |
| 7399274 |
Sensor configuration for a capsule endoscope |
July 15, 2008 |
| The present invention provides a capsule endoscope (CE) having sensors configured to form or to conform to the shell of the CE. The sensors are curved to correspond to the capsule's shape. According to this embodiment, the sensors may be covered by a coating material to protect the s |
| 7397677 |
Apparatus and method for charge pump control with adjustable series resistance |
July 8, 2008 |
| A charge pump is provided. The charge pump may include an oscillator, a first switch, a second switch, a capacitor/switch network, an error amplifier, an adjustable resistance circuit, a first switch driver, and a second switch driver. In one embodiment, the first and second drivers |
| 7397296 |
Power supply detection circuit biased by multiple power supply voltages for controlling a signal |
July 8, 2008 |
| A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a different |
| 7397292 |
Digital input buffer with glitch suppression |
July 8, 2008 |
| A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by the RC filter is p |
| 7397226 |
Low noise, low power, fast startup, and low drop-out voltage regulator |
July 8, 2008 |
| A circuit and method for providing voltage regulation that operates with relatively low noise, low power, fast start up and low dropout. The invention includes a constant voltage reference that is coupled to a reference amplifier which amplifies the reference voltage to a selectable |
| 7396754 |
Method of making wafer level ball grid array |
July 8, 2008 |
| A manufacturing technique that involves embedding one or more semiconductor die into a support substrate and forming conductive traces that lead from die contact pads to redistributed contact pads on the support substrate. Active surfaces of the dice and a working surface of the supp |
| 7395286 |
Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio |
July 1, 2008 |
| A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the coun |
| 7394861 |
Apparatus for generating signal gain coefficients for a SIMO/MISO transceiver for providing pack |
July 1, 2008 |
| Apparatus and method for generating signal gain coefficients for use in packet data communication between a single-input-single-output (SISO) transceiver and a single-input-multiple-output/multiple-input-single-output (SIMO/MISO) transceiver. Coordinate rotation digital computation ( |
| 7394309 |
Balanced offset compensation circuit |
July 1, 2008 |
| Balanced offset compensation is provided for a differential amplifier circuit. Two sets of three switches are employed between respective inputs and outputs of the differential amplifier to shunt the outputs to the input terminals during auto-zeroing phase. By opening and closing dif |
| 7394133 |
Dual direction ESD clamp based on snapback NMOS cell with embedded SCR |
July 1, 2008 |
| In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolati |
| 7391190 |
Apparatus and method for three-phase buck-boost regulation |
June 24, 2008 |
| A buck-boost converter is provided. In buck-boost mode, the converter operates in at least three phases. In one phase, the inductor current ramps upward. In another phase, the inductor current ramps downward. In yet another phase, the inductor current remains at roughly the same non- |
| 7390722 |
System and method for using an oxidation process to create a stepper alignment structure on semi |
June 24, 2008 |
| An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, |
| 7390682 |
Method for testing metal-insulator-metal capacitor structures under high temperature at wafer le |
June 24, 2008 |
| A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor |
| 7388447 |
Integrated clock generator tolerant to device parameter variation |
June 17, 2008 |
| A method and circuit for stabilizing a frequency of a clock generator comprising a ring oscillator with respect to manufacturing process variations and a circuit temperature. A bias circuit comprising a current mirror and cascade circuits provides a compensated bias current based on |
| 7388432 |
Current feedback amplifier with extended common mode input range |
June 17, 2008 |
| A Current Feedback Amplifier (CFA) is arranged to receive an input signal having a common mode (CM) range that is greater than the voltage across the supply rails. The CFA contains a rail-to-rail output stage that is configured to output an output signal in response to the common mode |
| 7388423 |
Start-up circuit with folding current arrangement |
June 17, 2008 |
| A start-up circuit includes a long channel current generator, a subtracting reference current generator, and a gain scaling current mirror-circuit. The long channel current generator circuit uses a long channel transistor circuit that simulates a high value resistor to provide a low- |
| 7388421 |
Fused trim circuit with test emulation and reduced static current drain |
June 17, 2008 |
| A trim circuit that is operable to adjust (trim) a digital or analog output of another electronic circuit, e.g., a regulator, comparator, signal processor, and the like. The novel trim circuit includes two fuses that can be separately "blown" or severed in such a way as to provide a |
| 7388414 |
Wideband power-on reset circuit with glitch-free output |
June 17, 2008 |
| A chip is initialized by a power-on reset circuit, after a turned-on power supply has reached a voltage level sufficient for normal chip operation. Logic gating is used to provide a glitch-free trigger signal that prevents erroneous chip re-initialization due to VDD glitches, and to |
| 7388404 |
Driver circuit that limits the voltage of a wave front launched onto a transmission line |
June 17, 2008 |
| A driver circuit limits the magnitude of the initial wave front launched onto a transmission line to a voltage that is approximately one-half of the supply voltage. Thus, immediately after the initial wave front is reflected from an open circuit receiver, a voltage at the receiver is |
| 7388385 |
Wafer dicing system |
June 17, 2008 |
| A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers of metal, are measured before the saw street is cut. During and after the saw street is |
| 7388359 |
Constant current output using transconductance amplifier |
June 17, 2008 |
| An apparatus in an electronic device such as a buck converter circuit receives as a first input a voltage signal VSNS from the electronic device that represents a current through the electronic device, and receives as a second input a direct current reference voltage signal from a re |
| 7387918 |
Method of forming a silicon controlled rectifier structure with improved punch through resistanc |
June 17, 2008 |
| When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantia |
| 7385426 |
Low current offset integrator with signal independent low input capacitance buffer circuit |
June 10, 2008 |
| A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transconductance amplifier device, and a third MOS transistor |
| 7385297 |
Under-bond pad structures for integrated circuit devices |
June 10, 2008 |
| An under bond pad structure is described for integrated circuit dice are that have active circuits located below at least some of the bond pads. The metallization layers interconnection structures within the die are arranged so that electrically conductive vias do not extend between the |
| 7382349 |
Methods and systems for determining display overdrive signals |
June 3, 2008 |
| A method of operating a display includes operating a pixel of the display using a first signal to provide a first brightness level. A characteristic of the first signal is represented by a value in a range extending from a minimum signal value to a maximum signal value. A second brig |
| 7381638 |
Fabrication technique using sputter etch and vacuum transfer |
June 3, 2008 |
| First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the opening. A physical sputter etch is performed on the |
| 7380151 |
Apparatus and method for asynchronously clocking the processing of a wireless communication sign |
May 27, 2008 |
| The invention is directed to an apparatus, method and system for providing reduced power consumption, fast processing of digitized communication signals and relatively easy reconfiguration for different applications, such as communication protocols/standards. The invention recognizes tha |
