| Patent Number |
Title Of Patent |
Date Issued |
| 7504888 |
Internally compensated differential amplifier |
March 17, 2009 |
| The invention relates to a differential amplifier with internal compensation. The invention also relates to a regulator controller and a regulator which includes such an amplifier. The amplifier includes a preamplifier circuit and a gain circuit. The frequency response of the amplifi |
| 7504810 |
Apparatus and method for generating a spread-spectrum clock for a switching regulator |
March 17, 2009 |
| A switching regulator circuit is provided. The switching regulator circuit includes an oscillator circuit which includes a capacitor, a switch, a comparator, a variable resistor, and a modulating signal generation circuit. The capacitor is arranged to receive a first current to provide |
| 7504783 |
Circuit for driving and monitoring an LED |
March 17, 2009 |
| Described herein is technology for, among other things, a circuit for controlling a current through an LED. The novel circuit includes a regulator for providing the current to the LED, an LED voltage monitoring circuit for monitoring a voltage drop across the LED and for providing a |
| 7504340 |
System and method for providing contact etch selectivity using RIE lag dependence on contact asp |
March 17, 2009 |
| A system and method is disclosed for providing contact etch selectivity for the etching of a plurality of contact etch holes through a dielectric layer of an integrated circuit. The method comprises the steps of obtaining a value of the reactive ion etch (RIE) lag for the dielectric |
| 7502568 |
Method of using low bandwidth sensor for measuring high frequency AC modulation amplitude |
March 10, 2009 |
| A slow monitor diode having a bandwidth only partially overlapping a lower end of a data transmission spectrum for a data transmission laser is employed to detect and control average output power of the data transmission laser and, from peak-to-peak measurements, optical modulation a |
| 7501860 |
Differential input driver using current feedback and cross-coupled common base devices |
March 10, 2009 |
| A differential input driver circuit (10, 50) includes first and second transistors (Q0, Q3) as input transistors and third and fourth transistors (Q1, Q2) as diode-connected, cross-coupled transistors. In one embodiment, first, second, third and fourth transistors are NPN bipolar tra |
| 7501859 |
Differential signaling system with signal transmission interruption following error detection |
March 10, 2009 |
| A differential signaling system in which errors in signal transmission or reception, or both, can be detected to allow signal transmission to be interrupted and thereby prevent further erroneous signal transmission or reception. |
| 7498874 |
Glitch-free start-up with a tracking pin |
March 3, 2009 |
| An error amplifier for closed loop operation is provided. The error amplifier has a track input and a feedback input. During soft-start, a voltage offset is added to the error amplifier input. In one embodiment, the voltage offset is gradually removed during the soft-start. |
| 7498845 |
Power supply switching at circuit block level to reduce integrated circuit input leakage current |
March 3, 2009 |
| Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is |
| 7498794 |
Method and system for sensing current independently of variations in operating conditions |
March 3, 2009 |
| A method for sensing current independently of variations in operating conditions is provided that includes generating a switch signal at a switching element. A reference signal is generated at a reference signal generator that is operable to track the switching element. A sense signal |
| 7498769 |
Apparatus and method for dual mode battery charger with linear and switched control modes based |
March 3, 2009 |
| A circuit for battery charging is provided. The circuit provides a charge current to a battery, and regulates the charge current with either linear regulation or switching regulation, based on operating conditions. In one embodiment, if the input voltage minus the battery voltage is less |
| 7495506 |
Headroom compensated low input voltage high output current LDO |
February 24, 2009 |
| A low-dropout regulator is provided. The low-dropout regulator includes a p-type depletion transistor as a pass device. The low-dropout regulator further includes switch circuitry and a charge pump that provides, at its output, a voltage greater than VDD. The source of the p-type depleti |
| 7495424 |
Overload compensation circuit with improved recovery response for a power supply |
February 24, 2009 |
| A compensation network for an error amplifier is provided. During normal operation, proportional-integral control is performed, and a capacitor of the compensation network is coupled to the error current. During a fault condition, the capacitor is de-coupled from the error current and |
| 7495423 |
Apparatus and method for loop adjustment for a DC/DC switching regulator |
February 24, 2009 |
| A current-mode switching regulator is provided. In one embodiment, the regulator is a multi-mode buck-boost regulator that operates as follows. When the operating mode changes, a gain associated with the inner current loop changes, and the loop compensation changes. The inner current loo |
| 7495419 |
Apparatus and method for PFM buck-or-boost converter with smooth transition between modes |
February 24, 2009 |
| A PFM buck-or-boost converter is provided. The converter includes, inter alia, a hysteretic comparator, current sense circuitry, a logic circuit, drivers, current sense circuitry, a first buck switch, and a first boost switch. The current sense circuitry asserts signal Z if the current |
| 7493149 |
Method and system for minimizing power consumption in mobile devices using cooperative adaptive |
February 17, 2009 |
| A method for minimizing power consumption in a mobile device using cooperative adaptive voltage and threshold scaling is provided that includes receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage. A clock signal is received. The clock signal is propaga |
| 7491625 |
Gang flipping for IC packaging |
February 17, 2009 |
| A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the |
| 7490279 |
Test interface for random access memory (RAM) built-in self-test (BIST) |
February 10, 2009 |
| Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algo |
| 7488647 |
System and method for providing a poly cap and a no field oxide area to prevent formation of a v |
February 10, 2009 |
| A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench a |
| 7486494 |
SCR with a fuse that prevents latchup |
February 3, 2009 |
| A chip which utilizes a silicon controlled rectifier (SCR) for ESD protection prevents a latchup condition from occurring when the SCR misfires and turns on during normal operation by utilizing a fuse in series with the SCR. The fuse allows the SCR to perform normally during an ESD e |
| 7486063 |
Versatile system for high-power switching controller in low-power semiconductor technology |
February 3, 2009 |
| The present invention provides a versatile system for providing a current-mode switching controller--in low voltage commercial semiconductor technologies--that is compatible with applications having very high input voltage ranges. The system provides an output transistor and a sense |
| 7485538 |
High performance SiGe HBT with arsenic atomic layer doping |
February 3, 2009 |
| A base structure for high performance Silicon Germanium (SiGe) based heterojunction bipolar transistors (HBTs) with arsenic atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas or hydrogen gas (in ambient temperature approximately equal |
| 7484143 |
System and method for providing testing and failure analysis of integrated circuit memory device |
January 27, 2009 |
| A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that |
| 7483683 |
Harmonic rejection gated-switching mixer |
January 27, 2009 |
| Rejection of local oscillator harmonic response is provided in a mixing circuit with a pair of harmonic gating switches serially connected to the outputs of a balanced differential switching mixer and controlled by a gate clock signal having twice the frequency of a local oscillator sign |
| 7483310 |
System and method for providing high endurance low cost CMOS compatible EEPROM devices |
January 27, 2009 |
| A system and method are disclosed for providing EEPROM devices that combine the high endurance features of complex and expensive EEPROM devices and the low manufacturing costs of CMOS compatible EEPROM devices. A memory cell of the invention comprises a control capacitor, an erase ca |
| 7482657 |
Balanced cells with fabrication mismatches that produce a unique number generator |
January 27, 2009 |
| A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-rando |
| 7482228 |
Method of forming a MOS transistor with a litho-less gate |
January 27, 2009 |
| The width of the gate of a MOS transistor can be formed to have nanometer-width gate sizes, which are substantially less than the minimum feature size that can be photolithographically obtained with the method that is used to fabricate the MOS transistors, in a litho-less process by |
| 7480190 |
Known default data state EPROM |
January 20, 2009 |
| An embodiment of the present invention is directed to a circuit for indicating the program status of an EPROM. The circuit includes a first and second transistor coupled to a first voltage potential. The circuit further includes a latching circuit coupled to the first and second tran |
| 7479831 |
Class AB differential current conveyor input stage for a fully differential current feedback amp |
January 20, 2009 |
| Disclosed herein is technology for, among other things, a current feedback fully differential amplifier. The amplifier includes an input stage operable to sense an input current at a first terminal and a second terminal. The input stage includes a first buffer having an input coupled |
| 7479812 |
Producing a frequency-representative signal with rapid adjustment to frequency changes |
January 20, 2009 |
| A feed-forward path is combined with a feed-back path to produce an output signal representation of an input signal frequency. The feed-forward path adjusts the output signal representation in response to a change in the input signal frequency, and does so in a response time that is |
| 7479778 |
Adaptive slope compensation for switching regulators |
January 20, 2009 |
| A system, method, and apparatus are arranged to provide adaptive slope compensation in a switching regulator that includes an inductor. A control loop of the switching regulator is responsive to a ramp signal. A ramp generator that includes a capacitor circuit and a current source pr |
| 7479768 |
System and method for providing variable gain loop control for use in adaptive voltage scaling |
January 20, 2009 |
| A system and method is disclosed for providing efficient closed loop feedback control in an adaptive voltage scaling system. The closed loop feedback circuitry of the invention comprises variable feedback gain for an error amplifier circuit. In one embodiment the variable feedback gain |
| 7479435 |
Method of forming a circuit having subsurface conductors |
January 20, 2009 |
| A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implante |
| 7479411 |
Apparatus and method for forming solder seals for semiconductor flip chip packages |
January 20, 2009 |
| An apparatus and method for forming a substantially continuous solder bump around the periphery of each dice on a flip chip wafer is disclosed. The solder bump is provided on each die so that when it is singulated from the wafer and mounted onto a substrate, the solder bump around the |
| 7479399 |
System and method for providing automated sample preparation for plan view transmission electron |
January 20, 2009 |
| A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing too |
| 7477886 |
Cascading-synchronous mixer and method of operation |
January 13, 2009 |
| A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency o |
| 7477113 |
Voltage-controlled capacitance linearization circuit |
January 13, 2009 |
| A linear voltage-controlled capacitance circuit is provided that includes a plurality of differentially coupled metal-oxide-semiconductor (MOS) varactor pairs. Each MOS varactor pair is operable to receive a same tuning voltage and to receive a bias voltage unique to the MOS varactor |
| 7477077 |
Apparatus and method for loss of signal detection in a receiver |
January 13, 2009 |
| An apparatus, device, and method for loss of signal detection in a receiver are provided. A reference circuit is operable to rectify a reference signal. An input circuit is operable to rectify an input signal. A comparator is operable to compare outputs of the reference circuit and t |
| 7474230 |
RFID temperature logger incorporating a frequency ratio digitizing temperature sensor |
January 6, 2009 |
| A semi-passive radio frequency identification (RFID) tag being coupled to a battery providing a battery voltage for powering a part of the circuitry of the RFID tag includes an RF communication block receiving and transmitting RF signals, a sensor block including a frequency ratio di |
| 7474154 |
Bias device clamping circuit for fast over-range recovery |
January 6, 2009 |
| A gain-boosted telescopic amplifier (100) includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (M.sub.P1, M.sub.N1), a pair of NMOS gain-boosted cascode |
| 7474133 |
Apparatus and method for high-speed serial communications |
January 6, 2009 |
| An apparatus, device, and method for high-speed serial communications are provided. An input circuit is operable to receive an input signal, where the input circuit includes transistors forming (i) a first differential pair associated with a first current source and (ii) a second dif |
| 7472305 |
Method and apparatus for limiting the output frequency of an on-chip clock generator |
December 30, 2008 |
| Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the reference clock input signal frequency with minimum and maximum calibration word signals, |
| 7472030 |
Dual mode single temperature trimming |
December 30, 2008 |
| In a system for performing a dual mode single temperature trim upon an electronic device to remove combined mismatch and process variation errors, a dynamic element matching control is configured for enabling dynamic element matching of components of the electronic device. A process |
| 7471572 |
System and method for enhancing erase performance in a CMOS compatible EEPROM device |
December 30, 2008 |
| A system and method are disclosed for enhancing the performance of erase operations in CMOS compatible EEPROM memory cells. An EEPROM memory cell is described in which the erase voltage and the coupling ratio of the EEPROM memory cell are simultaneously decreased while maintaining the |
| 7471218 |
Methods and systems for efficiently storing and retrieving streaming data |
December 30, 2008 |
| Various technologies for efficiently storing and retrieving streaming data are described. Bits of data (e.g., P bits of data) are received and separated into most significant bits (MSB) of data and least significant bits (LSB) of data. Further, the MSB of data and the LSB of data are |
| 7470978 |
Sawn power package and method of fabricating same |
December 30, 2008 |
| In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a portion o |
| 7470594 |
System and method for controlling the formation of an interfacial oxide layer in a polysilicon e |
December 30, 2008 |
| A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the em |
| 7470553 |
Built-in design edit structures |
December 30, 2008 |
| In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy forming vias through the passivation layer overlying the top metal layer and forming m |
| 7468899 |
Apparatus and method for wafer level fabrication of high value inductors on semiconductor integr |
December 23, 2008 |
| An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive |
| 7468895 |
Method and system for providing a bias voltage for a power input sub-circuit of a switched mode |
December 23, 2008 |
| A switched mode power supply (SMPS) is disclosed. The switched mode power supply (SMPS) includes a controller sub-circuit that generates an output signal that drives a switch. The controller sub-circuit generates a bias voltage without using a bias regulator for a sub-circuit of the swit |
