| Patent Number |
Title Of Patent |
Date Issued |
| 6905929 |
Single poly EPROM cell having smaller size and improved data retention compatible with advanced |
June 14, 2005 |
| Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate |
| 6903979 |
Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of subs |
June 7, 2005 |
| A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential |
| 6903978 |
Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of c |
June 7, 2005 |
| A method of programming a PMOS stacked gate memory cell is provided that utilizes a sequence of control gate pulses to obtain the desired potential on the floating gate. |
| 6903601 |
Reference voltage generator for biasing a MOSFET with a constant ratio of transconductance and d |
June 7, 2005 |
| An integrated circuit (IC) with metal oxide semiconductor field effect transistor (MOSFET) circular for generating a reference signal having a value which remains substantially constant over variations in one or more of the processing (P) of, power supply voltage (V) for and operating |
| 6903558 |
Digitizing ohmmeter system |
June 7, 2005 |
| A digitizing ohmmeter system for providing a digital resistance measurement includes a current source for providing an excitation current to an impedance-varying input sensor and an ADC circuit including a charge-balancing modulator and a digital post processing circuit. The system u |
| 6900697 |
Method and system for providing power management in a radio frequency power amplifier by dynamic |
May 31, 2005 |
| A method for providing power management in a radio frequency power amplifier is provided. An input voltage is received. A digital power supply signal is generated. From the input voltage, a regulated power supply signal is generated based on the digital power supply signal. |
| 6900669 |
Area efficient on-chip timeout generator with low temperature and low supply voltage dependency |
May 31, 2005 |
| An area-efficient fully integrated BiCMOS analog time delay circuit with low-power supply requirements provides delays as long as two milliseconds. An ultralow PTAT current source comprises medium-value resistors to discharge an on-chip capacitor from a fixed zero-temperature coefficient |
| 6900532 |
Wafer level chip scale package |
May 31, 2005 |
| A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit |
| 6900110 |
Chip scale package with compliant leads |
May 31, 2005 |
| A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connec |
| 6897692 |
Charge pump using dynamic charge balance compensation circuit and method of operation |
May 24, 2005 |
| A charge pump comprises a first current mirror that injects a first charging current onto a loop filter and a second charging current onto an integrator capacitor. The first and second charging currents are controlled by a first common control signal. The first charging current mirro |
| 6894695 |
Apparatus and method for acceleration of 2D vector graphics using 3D graphics hardware |
May 17, 2005 |
| For use in a system capable of creating and displaying vector computer graphics, there is disclosed an apparatus and method for acceleration of 2D vector graphics using both a general purpose computer and conventional 3D graphics hardware. In one advantageous embodiment, the apparatus an |
| 6894537 |
Apparatus and method for level shifting in power-on reset circuitry in dual power supply domains |
May 17, 2005 |
| A level shifter for use in a dual power supply circuit operating from a VDD power supply and a VDDH power supply greater than the VDD power supply. The level shifter indicates to a status circuit in the VDDH power supply domain that the VDD power supply is enabled. The level shifter dete |
| 6894462 |
Ratio adaptive gated oscillator |
May 17, 2005 |
| The present invention can be employed with any power supply circuit where it is desirable to employ a ratio adaptive, gated oscillator based step up switching regulator with a selectable duty cycle. By selecting a particular value for a capacitor coupled between the regulator's Frequency |
| 6894376 |
Leadless microelectronic package and a method to maximize the die size in the package |
May 17, 2005 |
| Arrangements and methods of packaging integrated circuits in leadless leadframe packages configured for maximizing a die size are disclosed. The package is described having an exposed die attach pad and a plurality of exposed contacts formed from a common substrate material. The contacts |
| 6891905 |
Apparatus and method for FSK demodulation with integrated time and frequency tracking |
May 10, 2005 |
| An FSK receiver comprising: 1) demodulation circuitry for receiving an incoming FSK signal and generating a baseband signal comprising an amplitude modulated symbol stream of Logic 0 symbols and Logic 1 symbols having a data rate, R; 2) auto-correlation circuitry for sampling the bas |
| 6891574 |
High speed video mixer circuit |
May 10, 2005 |
| A video amplifier having an on-screen display (OSD) capability uses one channel of an OSD input video signal to generate a blanking signal for blocking output of a video signal. When the blanking signal is asserted, the OSD channels provide the on-screen display. The blanking signal is |
| 6888765 |
Integrated circuit and method for testing same using single pin to control test mode and normal |
May 3, 2005 |
| An integrated circuit including operational circuitry operable in response to at least one control signal asserted to an external node from an external source, and test circuitry coupled to the external node and the operational circuitry. In response to data asserted to the external node |
| 6888383 |
Open loop LED driver system |
May 3, 2005 |
| A switching regulator circuit is arranged to provide a constant current to a load. The switching regulator circuit is operated in discontinuous current mode such that an inductor stores energy in a first part of an oscillation cycle, and discharges in a second part of the cycle. The |
| 6888228 |
Lead frame chip scale package |
May 3, 2005 |
| In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediate |
| 6881943 |
Convex image sensor and method of forming the sensor |
April 19, 2005 |
| An image sensor has a core structure with a convex surface, such as a sphere or a tube. The image sensor also has an interconnect layer that is adhered to the convex surface of the core structure, and a photo-sensing layer that is connected to the interconnect layer. The photo-sensing la |
| 6881895 |
Radio frequency (RF) filter within multilayered low temperature co-fired ceramic (LTCC) substrat |
April 19, 2005 |
| A multilayered, low temperature co-fired ceramic (LTCC) substrate within which a radio frequency (RF) filter is formed. Portions of a bandpass filter are implemented using electrode patterns on different ceramic tape layers of which selected portions are mutually superimposed, thereby |
| 6880099 |
Method and apparatus not requiring a clock signal for sampling an input signal |
April 12, 2005 |
| An input signal with an associated pulse width can be sampled using a sampling method that does not require a clock signal. The input signal is compared to a reference level signal to produce a comparator output signal. Strobe signals are generated from the input signal, where the st |
| 6879194 |
Apparatus and method for an active power-on reset current comparator circuit |
April 12, 2005 |
| An active power-on reset (POR) current comparator circuit creates a POR signal for resetting logic devices and masking reference startup signals during the initial power supply ramp of an integrated circuit. The comparator circuit provides a logic level signal (i.e., the POR signal) |
| 6877033 |
Network-based integrated device identification and ordering system |
April 5, 2005 |
| Techniques are provided for designing a circuit that satisfies user-specified functional requirements without the user having to obtain additional education or possess specialized software. According to one embodiment, user-specified functional requirements are received over a networ |
| 6876844 |
Cascading-synchronous mixer and method of operation |
April 5, 2005 |
| A radio frequency (RF) demodulation circuit comprising: 1) a radio frequency (RF) mixer having a first input port capable of receiving an incoming RF signal having a frequency of RF and a second input port capable of receiving a first local oscillator (LO) signal having a frequency o |
| 6876182 |
MOSFET current mirror circuit with cascode output |
April 5, 2005 |
| A metal oxide semiconductor field effect transistor (MOSFET) current mirror circuit with a cascode output in which maximum operating ranges are achieved for the power supply voltage and cascode output biasing voltage. Replica biasing ensures adequate biasing for the cascode driver tr |
| 6876052 |
Package-ready light-sensitive integrated circuit and method for its preparation |
April 5, 2005 |
| A package-ready light-sensitive integrated circuit and process for preparing a light-sensitive semiconductor substrate for packaging that provide for a reduced exposure of a light-sensitive integrated circuit to light. The package-ready light-sensitive integrated circuit includes a s |
| 6874933 |
Apparatus for digital temperature measurement in an integrated circuit |
April 5, 2005 |
| A circuit for measuring temperature with all digital components in an integrated circuit. During manufacture, the number of clock period cycles during a known period of time at a predetermined temperature is stored in non-volatile memory. Later, during use of the integrated circuit, a cl |
| 6873670 |
Automatic pre-scaler control for a phase-locked loop |
March 29, 2005 |
| A phase locked loop (PLL) system is arranged to automatically adjust the pre-scaler divide ratio. The PLL includes a phase-frequency detector circuit that compares a feedback clock signal to an input clock signal to provide UP and DOWN signals. A charge-pump circuit provides an oscillato |
| 6873318 |
Method and apparatus for addressing beat patterns in an integrated video display system |
March 29, 2005 |
| Disclosed is a video data re-clocking scheme for use in highly integrated system circuits to overcome the problem of beat patterns. These type of circuits contain many subsystem blocks, and each of those blocks may use different clock frequencies. Due to implementation constraints, clock |
| 6873228 |
Buried self-resonant bypass capacitors within multilayered low temperature co-fired ceramic (LTC |
March 29, 2005 |
| A multilayered, low temperature co-fired ceramic (LTCC) substrate within which one or more capacitors are formed (e.g., for power supply decoupling). Self-resonance is introduced by the capacitance of each capacitor interacting with an inductance formed by the interconnects (e.g., co |
| 6872962 |
Radio frequency (RF) filter within multilayered low temperature co-fired ceramic (LTCC) substrat |
March 29, 2005 |
| A multilayered, low temperature co-fired ceramic (LTCC) substrate within which a radio frequency (RF) filter is formed. Portions of a bandpass filter are implemented using electrode patterns on different ceramic tape layers of which selected portions maintain a symmetrical physical filte |
| 6872599 |
Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
March 29, 2005 |
| Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are prov |
| 6871309 |
Verification of redundant safety functions on a monolithic integrated circuit |
March 22, 2005 |
| A method and apparatus for verifying that redundant circuits are truly redundant is provided. Extra circuitry is included within the integrated circuit to test the features of a chip. Without testing of the redundant fictions on the circuit, true redundancy of the functions contained on |
| 6870569 |
Integrated multilevel signal demultiplexor |
March 22, 2005 |
| An integrated circuit with a signal demultiplexor for separating out two signals of different magnitudes from within a multiplexed signal without requiring a large capacitance for signal filtering. A multiple-threshold input comparator stage separates the multiplexed input signal into a |
| 6870410 |
All digital power supply system and method that provides a substantially constant supply voltage |
March 22, 2005 |
| An all digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes an up/down counter and a pulse width modulator to output a signal into a LC network that generates the supply voltage. The width of the pulses output by the pulse |
| 6870357 |
Method and apparatus for determining the temperature of a junction using voltage responses of th |
March 22, 2005 |
| Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes the voltage response of the junction to the at least two currents is measured and the temperature |
| 6869216 |
Digitizing temperature measurement system |
March 22, 2005 |
| A digitizing temperature measurement system for providing a digital temperature measurement includes an excitation source for providing switched excitation currents to two or three temperature sensing elements and an ADC circuit including a charge-balancing modulator and a digital po |
| 6868503 |
Adaptive voltage scaling digital processing component and method of operating the same |
March 15, 2005 |
| There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a c |
| 6867573 |
Temperature calibrated over-current protection circuit for linear voltage regulators |
March 15, 2005 |
| An apparatus and method provide for temperature calibrating an over-current limit in a linear regulator. Output current is delivered to the load through a power pass device that is responsive to a gate control signal. A transistor circuit provides a sense current that is proportional to |
| 6867470 |
Multi-slope analog temperature sensor |
March 15, 2005 |
| The present invention provides a temperature sensor that has high sensitivity and operates in a wide range of temperatures and VDD levels. The temperature sensor may be tailored to the application according to the conditions of temperature and VDD. The temperature sensor comprises five |
| 6864600 |
Apparatus and method for providing multiple power supply voltages to an integrated circuit |
March 8, 2005 |
| There is disclosed an apparatus and method for providing multiple power supply voltages to an integrated circuit. In an integrated circuit of the type comprising at least two power supply domains in which each power supply domain comprises at least one module powered by the same voltage |
| 6864581 |
Etched metal trace with reduced RF impendance resulting from the skin effect |
March 8, 2005 |
| The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q. |
| 6864167 |
Wafer scale solder bump fabrication method and structure |
March 8, 2005 |
| A process and structure for the wafer scale fabrication of packaged semiconductor dies having solder bumps of less than about 300 .mu.. A method of forming solder bump electrical connections to electrical contact pads for semiconductor dies includes providing a semiconductor wafer ha |
| 6863450 |
Optical sub-assembly packaging techniques that incorporate optical lenses |
March 8, 2005 |
| Techniques for manufacturing an optical transmission device in a manner so that the photonic device is protected from damage that can be caused by exposure to the environment and physical handling are described. The invention involves placing a lens or a lens array over a photonic device |
| 6862720 |
Interconnect exhibiting reduced parasitic capacitance variation |
March 1, 2005 |
| Adjacent metal lines of an interconnect metallization layer exhibit reduced variation in parasitic capacitance due to the presence of an intervening third metal line. The third metal line is electrically linked to one of the adjacent metal lines and is designed to project into the space |
| 6862216 |
Non-volatile memory cell with gated diode and MOS transistor and method for using such cell |
March 1, 2005 |
| A non-volatile memory cell including a gated diode and a single readout transistor, methods for programming and reading out such a cell, and a memory including an array of such cells. The readout transistor is an MOS transistor. The transistor and gated diode are formed in a volume of |
| 6861886 |
Clock deskew protocol using a delay-locked loop |
March 1, 2005 |
| A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. Th |
| 6861881 |
Fractional clock divider using digital techniques |
March 1, 2005 |
| A fractional clock divider system and method is provided. The clock divider is configured to provide an output clock signal in response to an input clock signal. The frequency of the output clock signal may be an integral or fractional division of the input clock signal. The output frequ |
| 6861306 |
Method of forming a split-gate memory cell with a tip in the middle of the floating gate |
March 1, 2005 |
| A split-gate FLASH memory cell is formed with a floating gate that has a tip in the middle of the floating gate. The method of the present invention forms the tip to have a substantially constant radius of curvature, tip angle, and distance to the overlying tunneling oxide. As a resu |
