| Patent Number |
Title Of Patent |
Date Issued |
| 7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level |
August 25, 2009 |
| An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same |
| 7581131 |
Method and system for balancing clock trees in a multi-voltage synchronous digital environment |
August 25, 2009 |
| A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain. Similarly, a second source clock signal is |
| 7581120 |
System and method for providing multi-point calibration of an adaptive voltage scaling system |
August 25, 2009 |
| A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the a |
| 7580428 |
3GPP WCDMA receiver using pipelined apparatus and method for performing cell searches |
August 25, 2009 |
| A pipelined cell search apparatus having a primary search stage, a secondary stage and a Gold code stage. The primary stage receives a primary synchronization channel (P-SCH) signal, detects a maximum peak of a slot boundary in the P-SCH signal, and generates slot timing data from th |
| 7579906 |
System and method for providing a low power low voltage data detection circuit for RF AM signals |
August 25, 2009 |
| A system and method is disclosed for demodulating RF amplitude modulated signals in a demodulator circuit of an EPC0 compliant RFID tag. One advantageous embodiment of the invention comprises first and second input ports, a +ve envelope detector circuit for each of the first and second |
| 7579819 |
Apparatus and method for flywheel current injection for a regulator |
August 25, 2009 |
| A constant on-time regulator that may use a capacitor with low ESR without needing a series resistor is provided. A capacitor is employed to AC-couple a current sense voltage into the reference signal to provide a modified reference signal. The comparator compares the feedback voltage |
| 7579683 |
Memory interface optimized for stacked configurations |
August 25, 2009 |
| A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of |
| 7579642 |
Gate-enhanced junction varactor |
August 25, 2009 |
| A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. |
| 7573327 |
Autozeroing current feedback instrumentation amplifier |
August 11, 2009 |
| An embodiment of the present invention is directed to an instrumentation amplifier. The amplifier includes a first amplification sub-circuit, which includes an input stage for sensing a differential input and generating an intermediate current based thereon, a feedback stage, and an |
| 7573252 |
Soft-start reference ramp and filter circuit |
August 11, 2009 |
| A method and circuit for providing a controlled ramping and filtering to a reference voltage in a regulator circuit such that an inrush current is limited and noise coupling to an output voltage is reduced. In a typical regulator circuit a soft-start and filter circuit is inserted betwee |
| 7572708 |
Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structu |
August 11, 2009 |
| A bipolar transistor device architecture and method of manufacture uses doped glass on the sidewall of the emitter window opening to reduce the emitter-base overlap capacitance while at the same time improving the polysilicon plugging effect. The doped glass sidewall also improves do |
| 7571360 |
System and method for providing a clock and data recovery circuit with a fast bit error rate sel |
August 4, 2009 |
| A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create |
| 7570847 |
Method of forming an optical switch |
August 4, 2009 |
| A method of forming an optical switch is disclosed. The optical switch is implemented with one or more cantilevered optical channels, which are formed in a flexible waveguide structure, and an actuator which is connected to the cantilevered optical channels, to position the cantileve |
| 7570039 |
Apparatus and method for control supply output voltage techniques to track battery voltage |
August 4, 2009 |
| A voltage regulation and battery charging system is provided. The system can simultaneously provide a regulated output voltage and charge a battery. The system includes a battery charger circuit, a voltage regulator circuit, and a voltage tracking circuit. A voltage divider is used t |
| 7570033 |
Apparatus and method for PWM buck-or-boost converter with smooth transition between modes |
August 4, 2009 |
| A PWM buck-or-boost converter is provided. The converter includes an error amplifier, a rectifier/splitter, a first comparator, and a second comparator. The rectifier/splitter provides two signals proportional to the departure of the error voltage from a central value but increasing in |
| 7570020 |
Apparatus and method for magnetic charger IC for batteries with recycling of the LC filter for r |
August 4, 2009 |
| A voltage regulation and battery charging system is provided. The system may include a switching regulator selection control circuit, two switching regulator controller circuits, two power transistors, a common synchronous transistor, a common LC circuit, and a battery charger circui |
| 7567125 |
Differential amplifier with multiple signal gains and wide dynamic range |
July 28, 2009 |
| A circuit and method for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in |
| 7567071 |
Current and voltage source that is unaffected by temperature, power supply, and device process |
July 28, 2009 |
| An integrated circuit in accordance with one embodiment of the invention includes an oscillator circuit and a source circuit. The source circuit outputs a reference voltage and a bias current, wherein the reference voltage changes by substantially the same proportion as the bias current. |
| 7567063 |
System and method for minimizing power consumption of a reference voltage circuit |
July 28, 2009 |
| A system and method is disclosed for minimizing power consumption in a reference voltage circuit. A capacitor is coupled to a reference voltage circuit and charged to a voltage that equals the reference voltage of the reference voltage circuit. The capacitor is then decoupled from the |
| 7566626 |
System and method for providing a fully self aligned bipolar transistor using modified cavity fo |
July 28, 2009 |
| A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a |
| 7564454 |
Methods and displays having a self-calibrating delay line |
July 21, 2009 |
| A driver arrangement for a display includes at least one driver, such as a column driver, and a delay line arrangement coupled to the driver. The delay line arrangement delays a data signal provided to the driver by a delay period selectable from a plurality of possible delay periods. Th |
| 7564308 |
Self-biased operational amplifier |
July 21, 2009 |
| An operational amplifier in accordance with one embodiment of the invention includes folded cascode transistors and a self-biased common-mode feedback circuit coupled to the folded cascode transistors. The operational amplifier can include an output stage coupled to the self-biased c |
| 7564130 |
Power micro surface-mount device package |
July 21, 2009 |
| A semiconductor device is provided, which comprises: a die including an active surface; a multiplicity of bond pads formed on the active surface of the die, wherein a first one of the bond pads is larger than a second one of the bond pads; and a multiplicity of solder bumps, each formed |
| 7561084 |
Sliding error sampler (SES) for latency reduction in the ADC path |
July 14, 2009 |
| A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value b |
| 7560958 |
Low power comparator with fast propagation delay |
July 14, 2009 |
| A direct relationship exists between an integrated comparator's propagation delay and the input differential pair's bias current and overdrive voltage. A new method using a pulsed bias scheme for the input differential pair improves propagation delay by more than one order of magnitu |
| 7560899 |
Circuit and method for adjusting safety time-out with charge current |
July 14, 2009 |
| A method and circuit for adjusting a safety time-out in charging devices based on a charge current. According to one embodiment, a signal that is based on the charge current is employed to control an output of an oscillator, which controls an operation of a safety timer circuit. The |
| 7560898 |
Apparatus and method for dual source, single inductor magnetic battery charger |
July 14, 2009 |
| A voltage regulation and battery charging system is provided. The system may include a switching regulator selection control circuit, two switching regulator controller circuits, two power transistors, a common synchronous transistor, and a common LC circuit. The two switching regula |
| 7560348 |
Method for designing and manufacturing a PMOS device with drain junction breakdown point located |
July 14, 2009 |
| A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum |
| 7558969 |
Anti-pirate circuit for protection against commercial integrated circuit pirates |
July 7, 2009 |
| Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associ |
| 7558720 |
Dynamic computation of ESD guidelines |
July 7, 2009 |
| An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occ |
| 7557455 |
System and apparatus that reduce corrosion of an integrated circuit through its bond pads |
July 7, 2009 |
| A bond pad structure has a first conductive layer and an anti-reflective coating layer disposed on the first conductive layer. The first conductive layer includes first and second portions (which could be formed by etching). Part of the first portion is exposed within a bond pad open |
| 7555091 |
System and method for providing a clock and data recovery circuit with a self test capability |
June 30, 2009 |
| A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pa |
| 7554607 |
Video signal detection circuit |
June 30, 2009 |
| A signal detector for detecting and indicating the duration of a signal pulse by comparing the relative polarities of two voltages generated during the two states of the pulsed signal. |
| 7554408 |
Apparatus and method for asymmetric charge pump for an audio amplifier |
June 30, 2009 |
| An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD. |
| 7554403 |
Gainboost biasing circuit for low voltage operational amplifier design |
June 30, 2009 |
| Bias current generation circuits and systems are disclosed. In one embodiment, a gain boosting cascode system comprises a cascode based on a transconductance amplifier and a current buffer and a gain booster circuit coupled to the cascode optimally boosting a gain of the cascode by m |
| 7554387 |
Precision on chip bias current generation |
June 30, 2009 |
| Bias current generation circuits and systems are disclosed. In one embodiment, a bias current generation system comprises a current generation circuit generating a first current based on a first voltage and an external resistor, a current mirror forwarding a second current proportion |
| 7554377 |
Apparatus and method for signal voltage limiting |
June 30, 2009 |
| A circuit and method for limiting a signal voltage in which the minimum and maximum levels of the output signal can be controlled by selectively applying different lower and higher reference voltages from which the minimum and maximum output signal levels are derived. |
| 7554372 |
Digital dead-time controller for pulse width modulators |
June 30, 2009 |
| Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase sel |
| 7554313 |
Apparatus and method for start-up circuit without a start-up resistor |
June 30, 2009 |
| A start-up circuit is provided. In one embodiment, the start-up circuit operates as follows. In this embodiment, the start-up circuit includes a depletion-mode PMOS transistor and an NMOS switch. The NMOS switch is coupled between ground and a common gate node of a PMOS current mirror. |
| 7554152 |
Versatile system for integrated sense transistor |
June 30, 2009 |
| The present invention provides a versatile system for producing sense transistors having optimized thermal and parametric matching with an associated power transistor. A power transistor is formed, having a plurality of alternating source and drain structures, with a plurality of gat |
| 7551814 |
Optical detection of user interaction based on external light source |
June 23, 2009 |
| An apparatus for employing ambient light collected from an external light source to detect a user's fingers that are gripping at least a relatively transparent portion of a case. The ends of a plurality of waveguides are coupled at relatively unequal or equidistant positions to the inter |
| 7547618 |
System and method for providing a deep connection to a substrate or buried layer of a semiconduc |
June 16, 2009 |
| A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial s |
| 7546557 |
Systems and methods for reducing IR-drop noise |
June 9, 2009 |
| The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transisto |
| 7545874 |
Apparatus for pre-scaling data packets with multiple signal gain coefficients in a SIMO/MISO tra |
June 9, 2009 |
| Apparatus and method for use in packet data communication from a single-input-multiple-output/multiple-input-single-output (SIMO/MISO) transceiver to a single-input-single-output (SISO) transceiver. Coordinate rotation digital computation (CORDIC) circuitry is used to scale outgoing |
| 7545303 |
Sigma-delta difference-of-squares RMS-to-DC converter with forward and feedback paths signal squ |
June 9, 2009 |
| A sigma-delta difference-of-squares RMS-to-DC converter and method for performing such a conversion in which a square of an analog feedback signal is combined differentially with a square of an analog input signal, thereby producing an analog product signal that includes at least one |
| 7545302 |
Sigma-delta difference-of-squares RMS-to-DC converter with forward path multiplier |
June 9, 2009 |
| A sigma-delta difference-of-squares RMS-to-DC converter and method for performing such a conversion in which an analog feedback signal is combined with an analog input signal, following which the combined signals are multiplied to produce an analog product signal that includes at lea |
| 7545210 |
Gain adjustment for programmable gain amplifiers |
June 9, 2009 |
| A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the |
| 7545209 |
Gain adjustment for programmable gain amplifiers |
June 9, 2009 |
| A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the |
| 7545021 |
Apparatus and method for making integrated circuit packages having integrated circuits mounted o |
June 9, 2009 |
| Semiconductor package assemblies having integrated circuits mounted onto passive electrical components. The assemblies each include an inductor having a magnetic core and an wire wrapped around the magnetic core. An integrated circuit die is positioned either on or within a recess formed |
| 7544579 |
System and method for faceting the corners of a resistor protect layer to reduce vertical step h |
June 9, 2009 |
| A system and method is disclosed for providing a resistor protect layer to protect a thin film resistor in a semiconductor device. A thin film resistor is formed on a dielectric layer and a resistor protect layer is placed over the thin film resistor. An etch procedure is employed to |
