| Patent Number |
Title Of Patent |
Date Issued |
| 6963091 |
Spin-injection devices on silicon material for conventional BiCMOS technology |
November 8, 2005 |
| Spin-based microelectronic devices can be realized by utilizing ferromagnetic structures that make good ohmic contact with silicon, in order to avoid the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on si |
| 6962436 |
Digitizing temperature measurement system and method of operation |
November 8, 2005 |
| A digitizing temperature measurement system for providing a digital temperature measurement includes an excitation source for providing switched excitation currents to two or three temperature sensing elements and an ADC circuit including a charge-balancing modulator and a digital po |
| 6961634 |
System and method for allocating multi-function resources for a wetdeck process in semiconductor |
November 1, 2005 |
| A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a wetdeck process in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes at least one applicat |
| 6961400 |
Automatic frequency correction apparatus and method of operation |
November 1, 2005 |
| A frequency shift keyed (FSK) receiver for demodulating an incoming transmitted signal comprising: 1) a phase-locked loop for receiving an oscillator reference signal having a frequency F1 and generating a reference carrier frequency signal having a desired frequency N1(F1), wherein |
| 6960940 |
Short circuit protection apparatus with self-clocking self-clearing latch |
November 1, 2005 |
| A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a |
| 6960792 |
Bi-directional silicon controlled rectifier structure with high holding voltage for latchup prev |
November 1, 2005 |
| A bi-directional silicon controlled rectifier structure provides electrostatic discharge (ESD) protection against both positive and negative voltage spikes. The structure utilizes a pair of wells, n+ and p+ regions formed in both wells, a first ring formed around the junction between |
| 6959225 |
Graphical user interface for allocating multi-function resources in semiconductor wafer fabricat |
October 25, 2005 |
| A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a process system in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes at least one applicati |
| 6959179 |
Down/up-conversion mixer for direct conversion radios |
October 25, 2005 |
| A RF down/up-conversion circuit comprising: 1) a local oscillator chopping circuit comprising: a) a frequency divider circuit for receiving a first local oscillator (LO) signal having a frequency of LO and generating a frequency-divided second local oscillator (LO) signal having a freque |
| 6958720 |
Fine string compensation to minimize digital to analog converter differential nonlinearity error |
October 25, 2005 |
| Disclosed is a process for minimizing digital-to-analog converter differential nonlinearity by adjusting taps in resistive elements in a fine resistor string voltage divider circuit. Active buffer circuits can be eliminated while still minimizing DAC DNL and insuring circuit monotici |
| 6958712 |
Low gate count 3GPP channelization code generator |
October 25, 2005 |
| A channelization code is generated in response to a spreading factor and a code number. The code number is right justified to provide a right-justified code number. The right-justified code number is stored in an eight-bit register. An eight-bit binary counter is arranged to provide |
| 6958591 |
Battery charging safety circuit for simultaneous startup and rapid surge current clamping |
October 25, 2005 |
| A safety circuit monitors a charging signal supplied by a charging circuit for charging a battery. Damage to the battery may occur when the voltage at the input terminal of the battery rises above the safe level for the battery. A voltage drop across a coupling circuit is used to generat |
| 6958590 |
Temperature compensated battery charger current |
October 25, 2005 |
| A battery charger circuit is arranged to charge batteries in a constant current mode. A charging current flows from a power device through a sense resistor to a battery. The voltage across the sense resistor is used to measure the charging current. The temperature of the sense resistor |
| 6957910 |
Synchronized delta-VBE measurement system |
October 25, 2005 |
| A circuit in an integrated circuit for measuring temperature dependent voltages of a temperature sensing element includes a voltage generator circuit providing the temperature dependent voltages, a first sampling switch and a second sampling switch. The voltage generator circuit incl |
| 6957114 |
Graphical user interface for compliance monitoring in semiconductor wafer fabrication and method |
October 18, 2005 |
| A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a process system in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes at least one applicati |
| 6957113 |
Systems for allocating multi-function resources in a process system and methods of operating the |
October 18, 2005 |
| There are disclosed systems, as well as methods of operation, for allocating multi-function resources among a plurality of tasks within a process system. An exemplary resource allocator is introduced that allocates multi-function resources among tasks within a process system capable |
| 6956439 |
Transimpedance amplifier with controllable noise reduction |
October 18, 2005 |
| A transimpedance amplifier with controllable noise reduction in which DC offsets due to the input signal are tolerated during reception of low input signals by reducing, e.g., terminating, a compensation current to remove a dominant source of thermal noise, but compensated during rec |
| 6956411 |
Constant R.sub.ON switch circuit with low distortion and reduction of pedestal errors |
October 18, 2005 |
| A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, second and third switc |
| 6956291 |
Apparatus and method for forming solder seals for semiconductor flip chip packages |
October 18, 2005 |
| An apparatus and method for forming a substantially continuous solder bump around the periphery of each dice on a flip chip wafer is disclosed. The solder bump is provided on each die so that when it is singulated from the wafer and mounted onto a substrate, the solder bump around the pe |
| 6956269 |
Spin-polarization of carriers in semiconductor materials for spin-based microelectronic devices |
October 18, 2005 |
| Spin-based microelectronic devices can be realized by utilizing spin-polarized ferromagnetic materials positioned near, or embedded in, a semiconductor channel of a microelectronic device. Applying an electric field across the channel can cause carriers flowing through the channel to |
| 6954201 |
Data bus system and protocol for graphics displays |
October 11, 2005 |
| The present invention provides a point-to-point data bus architecture and a protocol for a graphics system. The TCON transmits the data to the column drivers using separate point-to-point data buses. Data may be transmitted to the column drivers during a horizontal blanking period result |
| 6954169 |
1/f noise, offset-voltage charge injection induced error cancelled op-amp sharing technique |
October 11, 2005 |
| The present invention provides an apparatus and method for reducing and canceling 1/f noise, offset voltage, and charge injection introduced in pipeline ADCs in conventional op-amp sharing techniques. The polarity of the residue signals is changed at each phase. During phase one, the |
| 6954059 |
Method and apparatus for output voltage temperature dependence adjustment of a low voltage band |
October 11, 2005 |
| Adjustment of the temperature dependence of the output voltage of a band gap circuit is achieved by intentionally mismatching currents flowing through nodes coupled to the inputs of an amplifier. Each node is coupled to a bipolar junction transistor and a resistor, such that an output |
| 6952784 |
Multi-source power switching circuit for Wake On LAN ethernet application |
October 4, 2005 |
| A power and power management signaling circuit in a network interface card (NIC) for all known Wake On LAN PCI bus configurations includes a single voltage regulator together with connections to a network-initiated power management recovery signal MPT.sub.-- PMEN from the network interfa |
| 6952333 |
ESD protection circuit for high-voltage, high DV/DT pads |
October 4, 2005 |
| A pad that experiences a high-voltage, high dV/dT signal during normal operation is prevented from falsely triggering by utilizing a bipolar transistor connected to the pad to provide ESD protection, and a MOS transistor connected to the bipolar transistor to turn off the bipolar tra |
| 6952121 |
Prescaling for dividing fast pulsed signal |
October 4, 2005 |
| Circuits, devices and methods are provided for dividing a fast pulse signal by an integer M. A dual modulus prescaler receives input pulses, counts them, and generates one prescaled pulse for every Qth input pulse. Q is a division modulus, and has a different value depending on a modulus |
| 6952106 |
E-beam voltage potential circuit performance library |
October 4, 2005 |
| Point-by-point image contrast values are generated from secondary electron collection during unbiased electron or ion beam bombardment of an integrated circuit (IC) in a vacuum environment to quantify the physical and electrical integrity of connections within the device. These values |
| 6952093 |
Adaptive small-signal compensation for switching regulators |
October 4, 2005 |
| A system, method, and apparatus are arranged to provide small-signal compensation in a switching regulator that includes an inductor. A zero adjustment circuit is included in the system to introduce at least one zero in the closed-loop transfer function associated with the regulator. |
| 6952039 |
ESD protection snapback structure for overvoltage self-protecting I/O cells |
October 4, 2005 |
| In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain. |
| 6950490 |
Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates n |
September 27, 2005 |
| A fault state detector for a ring counter is formed from unit current sources each switched under the control of a different one of the outputs of the ring counter. The currents switched in that manner are passed through a unit resistance to generate a voltage signal proportional to the |
| 6950097 |
Video display interface controller for host video display unit |
September 27, 2005 |
| A video display interface controller for a host video display unit in which control signals multiplexed with component video signals are extracted and routed according to included address information. Control data associated with one or more local addresses is used for initial processing |
| 6949972 |
Apparatus and method for current sink circuit |
September 27, 2005 |
| A current sink circuit includes a current mirror, a feedback circuit, a follower circuit, and a current sink. The current mirror includes a power transistor. Also, the current mirror is ratioed such that the drain current of the power transistor is significantly greater than the drain |
| 6949968 |
Method for increasing the sensitivity of integrated circuit temperature sensors |
September 27, 2005 |
| A method and apparatus are arranged to provide increased sensitivity for a temperature sensor in an integrated circuit such that the accurate temperature sensing is achieved over a broad temperature range. A temperature sense signal from a VPTAT circuit is coupled to a level shifter |
| 6949421 |
Method of forming a vertical MOS transistor |
September 27, 2005 |
| A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the |
| 6947331 |
Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal |
September 20, 2005 |
| A method is provided for erasing a nonvolatile memory cell that includes a source region, a drain region, a floating gate electrode and a control gate electrode to which an erase signal is applied. In accordance with the method, a source bias voltage is applied to the source region, a dr |
| 6947022 |
Display line drivers and method for signal propagation delay compensation |
September 20, 2005 |
| Methods and apparatus for compensating the effects of display signal propagation delay in a display panel are disclosed. The apparatus comprises circuitry in addition to conventional display driver circuitry for delaying display line timing signals by an amount approximating the dela |
| 6946904 |
USB with over-voltage and short-circuit protection |
September 20, 2005 |
| A transceiver circuit includes driver circuits, receiver circuits, and suspend-mode buffers that are arranged to withstand an over-voltage conditions that would otherwise damage those circuits. An over-voltage sense circuit is arranged to detect the over-voltage condition on a data l |
| 6946881 |
Method to detect the polarity of sync signals without external capacitor or clock |
September 20, 2005 |
| In a polarity detector circuit for detecting the polarity of monitor sync signals, a clock generator and counter circuit are provided to count clock cycles during the positive and negative portions of the signal. Comparators are used to compare the counter values to predetermined values |
| 6946706 |
LDMOS transistor structure for improving hot carrier reliability |
September 20, 2005 |
| An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electron |
| 6946690 |
High holding voltage ESD protection structure and method |
September 20, 2005 |
| The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by reducing the size of the p+ emitter defined by the LVTSCR-like device. As a resul |
| 6946321 |
Method of forming the integrated circuit having a die with high Q inductors and capacitors attac |
September 20, 2005 |
| A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electri |
| 6944780 |
Adaptive voltage scaling clock generator for use in a digital processing component and method of |
September 13, 2005 |
| There is disclosed clock control circuitry for selectively applying a clock signal to a digital processing component wherein the clock signal is capable of being changed to a plurality of operating frequencies. The clock control circuitry is operable to (i) receive a command to change a |
| 6943591 |
Apparatus and method for detecting a fault condition in a common-mode signal |
September 13, 2005 |
| The invention is directed to an apparatus and a method for generating a fault detection signal when a differential signal is in a fault condition. The fault condition arises when the data transmission path in a differential signaling device is either open, shorted, or terminated by an |
| 6943504 |
Open loop magnetic boost LED driver system and method |
September 13, 2005 |
| Current is delivered to a load using an open-loop boost circuit topology that is suitable for LED driver applications. An inductor in the circuit is charged when a transistor is active during a first operating phase. The inductor delivers current to the load when the transistor is inacti |
| 6940440 |
System and method for detecting when an external load is coupled to a video digital-to-analog co |
September 6, 2005 |
| A system and method for determining when an external load is coupled to a digital-to-analog converter (DAC). Specifically, in one embodiment, a load detector circuit comprises a video DAC, an output circuit, a dumping circuit, and a determining circuit. The video DAC comprises a differen |
| 6940358 |
Method and apparatus for tuning RF integrated LC filters |
September 6, 2005 |
| Using low impedance switches and coupling to a virtual ground, one or more capacitors are selectively switched into or out of an inductive-capacitive resonant circuit portion of an integrated circuit filter to alter the resonant frequency based on a phase difference between the resonant |
| 6940299 |
Method of testing for short circuits between adjacent input/output pins of an integrated circuit |
September 6, 2005 |
| In a method of testing an IC, short circuits between adjacent I/Os are tested by grounding alternate rows in one step, and alternate columns in another step, and, if necessary including a third step of testing any inadequately tested I/Os by identifying inadequately tested I/Os and then |
| 6940133 |
Integrated trim structure utilizing dynamic doping |
September 6, 2005 |
| An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals and a trapezoid shaped |
| 6939476 |
Method for real time metal ETCH critical dimension control |
September 6, 2005 |
| The present invention predicts Critical Dimension (CD) before processing a wafer lot and alters the etch by adjusting recipe inputs to control the current lots bias to target critical dimensions. Also, the process incorporates the use of etch chamber selection by an automated system, |
| 6937487 |
Apparatus and method for a voltage booster with improved voltage regulator efficiency |
August 30, 2005 |
| A power management system includes a voltage booster in combination with a voltage regulator to provide a regulated output voltage. The voltage provided to the voltage regulator is used to selectively enable/disable the doubling functionality of the voltage booster to increase power |
| 6937351 |
Non-destructive method of measuring the thickness of a semiconductor wafer |
August 30, 2005 |
| The thickness of a semiconductor wafer is non-destructively measured using infrared (IR) microscopy. The wafer is placed on a stage. A distance between the stage and a detector is then varied so that a first image of the wafer is focused on the detector. When focused, a first separation |
