| Patent Number |
Title Of Patent |
Date Issued |
| 7030598 |
Low dropout voltage regulator |
April 18, 2006 |
| A low dropout voltage regulator. The regulator comprises a bandgap reference circuit and first and second transistors coupled in parallel. The parallel transistors form the input of an operational amplifier, coupled to and providing substantially no load to the bandgap reference circ |
| 7029929 |
Method of manufacturing semiconductor devices using a bond program verification system |
April 18, 2006 |
| A method for checking a wire bonding recipe is provided. Generally, coordinate data of a master recipe is stored. Coordinate data of a slave recipe is stored. The coordinate data of the slave recipe is compared with coordinate data of the master recipe. An error signal is provided if |
| 7027278 |
Stacked high-voltage ESD protection clamp with triggering voltage circuit control |
April 11, 2006 |
| A stacked high-voltage ESD protection clamp is provided that realizes the desired triggering characteristics of a BJT or BSCR stacked snapback clamp. The operational principle of the new circuit is based upon introduction of a middle node capacitor into the stacked (cascoded) clamp. |
| 7027277 |
High voltage tolerant electrostatic discharge (ESD) protection clamp circuitry |
April 11, 2006 |
| High voltage tolerant electrostatic discharge (ESD) protection clamp circuitry including a self-triggering device having a blocking junction with a two-dimensional geometrical lateral profile. |
| 7024568 |
Method and system for providing self-calibration for adaptively adjusting a power supply voltage |
April 4, 2006 |
| A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. |
| 7024444 |
Split multiplier array and method of operation |
April 4, 2006 |
| There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split |
| 7023705 |
Ceramic optical sub-assembly for optoelectronic modules |
April 4, 2006 |
| Optoelectronic components, specifically, ceramic optical sub-assemblies are described. In one aspect, the optoelectronic component includes a ceramic base substrate having a pair of angled (or substantially perpendicular) faces. The electrical traces are formed directly on the cerami |
| 7023367 |
Current steering digital to analog converter with improved dynamic linearity |
April 4, 2006 |
| A current source cell includes a current source providing a first current at a first node where variations of a first voltage at the first node results in variations of the first current, and first and second switches coupled between the first node and respective first and second output |
| 7023227 |
Apparatus for socketing and testing integrated circuits and methods of operating the same |
April 4, 2006 |
| There is disclosed apparatus for socketing and testing integrated circuits, particularly RF and high-frequency integrated circuits in high density and fine pitch packages, and methods of operating the same. An exemplary apparatus includes an air machine and a housing. The housing inc |
| 7023074 |
Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
April 4, 2006 |
| Methods of fabricating leadless packages are described that provide good solder joint reliability. In most respects, the packages are fabricated in a manner similar to current lead frame based leadless packaging techniques. However, at some point in the process, the contacts are prov |
| 7023068 |
Method of etching a lateral trench under a drain junction of a MOS transistor |
April 4, 2006 |
| In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer. |
| 7023032 |
MOS transistor with serrated gate structures |
April 4, 2006 |
| A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by a |
| 7023029 |
Complementary vertical SCRs for SOI and triple well processes |
April 4, 2006 |
| In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provid |
| 7022968 |
Optical sensor that measures the light output by the combustion chamber of an internal combustio |
April 4, 2006 |
| An optical sensor provides information about the burn of the fuel mixture in the combustion chamber of an internal combustion engine as well as the timing and waveform of the spark that ignites the fuel mixture in the combustion chamber. The optical sensor can be implemented as a sta |
| 7022532 |
Method of making spin-injection devices on silicon material for conventional BiCMOS technology |
April 4, 2006 |
| Spin-based microelectronic devices can be realized by utilizing ferromagnetic structures that make good ohmic contact with silicon, in order to avoid the Schottky barrier problem plaguing existing approaches to spin-based microelectronics, while allowing the devices to be based on si |
| 7021151 |
MEMS pressure sensing array with leaking sensor |
April 4, 2006 |
| A pressure sensing system formed in a monolithic semiconductor substrate. The pressure sensing system comprises a pressure sensing device formed on the monolithic semiconductor substrate. Pressure sensing device is adapted to be disposed in an environment for developing an electrical |
| 7020027 |
Programming method for nonvolatile memory cell |
March 28, 2006 |
| A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node. |
| 7019678 |
Digital-to-analog converter with constant differential gain and method |
March 28, 2006 |
| A digital-to-analog converter is provided that includes an input stage and an output stage. The input stage is operable to receive a digital bit of data, to convert the digital bit into a quasi-differential current, and to convert the quasi-differential current into a first voltage using |
| 7019590 |
Self-stabilizing differential load circuit with well controlled impedance |
March 28, 2006 |
| A circuit for providing a self-stabilizing, differential load circuit with well controlled impedance to an amplifier is described. According to one embodiment, two pairs of transistors in a cross-coupled configuration and a degeneration resistor for each transistor provide the self-stabi |
| 7019581 |
Current sense circuit |
March 28, 2006 |
| A method and circuit for tracking a load current and a load voltage to provide an output signal that is proportional to the load current. The circuit enables employment of high gate area (W/L) ratio for a current mirror type current sense circuit, while maintaining accuracy of a sense |
| 7017127 |
Method and system for enabling energy efficient wireless connectivity |
March 21, 2006 |
| The invention is directed to a system and method that enables several different factors associated with the implementation of a particular wireless application to be considered in the design of an energy efficient wireless connectivity solution for an integrated circuit. Factors rega |
| 7016695 |
Apparatus and method for processing a deterministic data flow associated with a wireless communi |
March 21, 2006 |
| The invention is directed to an apparatus, method and system for providing reduced power consumption, fast processing of digitized communication signals and relatively easy reconfiguration for different applications, such as communication protocols/standards. The invention recognizes tha |
| 7015749 |
Frequency discriminator using replica compensated delay lines and method of operation |
March 21, 2006 |
| A frequency discriminator for detecting phase shifts between sequential pulses in a frequency-shift keyed (FSK) signal having a nominal frequency, f. The frequency discriminator comprises: 1) a first current controlled delay line for receiving the FSK signal and delaying the FSK sign |
| 7015746 |
Bootstrapped bias mixer with soft start POR |
March 21, 2006 |
| A biasing circuit is arranged to provide relatively well controlled startup and steady state behavior for a reference circuit such as noise immunity and reduced dependence on supplies. The biasing circuit initially employs an independent bias current for biasing the reference circuit |
| 7015745 |
Apparatus and method for sensing current in a power transistor |
March 21, 2006 |
| A circuit for regulating a sensed current in a power transistor is provided. The circuit is configured to sense if the drain current of the power transistor has reached a limit current I.sub.limit. A sense transistor is arranged in an m:1 current mirror relationship with the power tr |
| 7015744 |
Self-regulating low current watchdog current source |
March 21, 2006 |
| A self-regulating current source is formed by a PMOS current mirror and an interconnected pair of NMOS transistors. The NMOS transistors are sized differently and forced to operate at similar currents. The difference of the Vgs voltages of the NMOS transistors is impressed across the res |
| 7015732 |
Power-on reset circuit with low standby current and self-adaptive reset pulse width |
March 21, 2006 |
| A power-on reset circuit for an integrated circuit includes a voltage threshold detector circuit for generating a first signal, a DC biasing start-up circuit providing start-up currents and a first control signal, a self-regulating watchdog current source providing bias currents and a |
| 7015729 |
Apparatus and method for sample-and-hold with boosted holding switch |
March 21, 2006 |
| A pipelined sample-and-hold circuit is provided. The circuit is pipelined such that processing of a held signal can continue into the next sample phase. Also, the pipelined sample-and-hold circuit includes a hold switch. The hold switch includes a boosted switch and dummy circuits. The |
| 7015587 |
Stacked die package for semiconductor devices |
March 21, 2006 |
| A stacked multi-chip package is described in which a base die is electrically connected to both an interconnect structure (e.g., a lead frame or a substrate) and a stacked die. A first encapsulant is used to cover some, but not all of the bond pads on a base die as well as portions o |
| 7015064 |
Marking wafers using pigmentation in a mounting tape |
March 21, 2006 |
| Wafer level techniques for marking the back surfaces of integrated circuit devices are described. A wafer mounting tape is provided that includes releasable pigments. The pigments can be released by exposing the mounting tape to a selected frequency of electromagnetic radiation (e.g., |
| 7012282 |
Bumped integrated circuits for optical applications |
March 14, 2006 |
| An optical integrated circuit application where the integrated circuit is packaged in a clear molding material and is attached to a printed circuit board having an aperture is described. The integrated circuit senses and/or emits light through the clear molding material and through the |
| 7006800 |
Signal-to-noise ratio (SNR) estimator in wireless fading channels |
February 28, 2006 |
| A signal-to-noise estimator is provided for estimating the signal-to-noise ratio in wireless fading channels. The estimator can be applied to likelihood ratio estimation of turbo decoders in third generation wide-band code division multiple access (WCDMA) systems. Time-multiplexed sa |
| 7005728 |
Lead configuration for inline packages |
February 28, 2006 |
| A substrate for use in an inline IC package is designed such that its die attach pad and leads each have a number of protrusions and recesses. These protrusions and recesses create an irregular surface that provides better adhesion to encapsulant material than conventional leads and die |
| 7005388 |
Method of forming through-the-wafer metal interconnect structures |
February 28, 2006 |
| A semiconductor die is formed in a process that forms a hole through the wafer prior to the formation of the contacts and the metal-1 layer of an interconnect structure. The through-the-wafer hole is formed by using a wafer with a <110> crystallographic orientation and a wet etch, |
| 7002427 |
Filter trimming |
February 21, 2006 |
| An adjustable phase shifter generates a phase shifted reference signal by introducing a phase shift in a reference signal. A phase detector identifies a phase difference between the reference signal and the phase shifted reference signal. A control signal generator generates a plural |
| 7002326 |
Method of modulating current regulation control loop's current magnitude from a second control s |
February 21, 2006 |
| The present invention provides current regulation. The circuit includes a current regulation loop that includes a second control signal that is used to adjust the magnitude of the regulated current. The second control signal provides a signal that regulates the amount of current being |
| 7002241 |
Packaging of semiconductor device with a non-opaque cover |
February 21, 2006 |
| Packages of semiconductor devices with non-opaque covers and methods for making the packages. The invention allows an encapsulant to be used with a non-opaque cover. By ensuring the cover is attached to a die in such a way as to expose bonding pads while sealing in the imaging portion of |
| 7002239 |
Leadless leadframe packaging panel featuring peripheral dummy leads |
February 21, 2006 |
| Methods and apparatuses for providing leadless leadframes with dummy contact leads are disclosed. A leadframe is described that includes an enclosed frame having two lengthwise portions and two widthwise portions. The leadframe also includes a device area array with dummy contact leads |
| 7001083 |
Technique for protecting photonic devices in optoelectronic packages with clear overmolding |
February 21, 2006 |
| This disclosure describes a clear overmolding cap for protecting the photonic devices in optoelectronic packages from damage due to handling, module assembly, board assembly, and environmental exposure in field applications. The overmolding of the devices with a clear mold cap or sim |
| 7000132 |
Signal-initiated power management method for a pipelined data processor |
February 14, 2006 |
| A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal. |
| 7000128 |
Method and apparatus for reducing capacitive load-related power loss by gate charge adjustment |
February 14, 2006 |
| The present invention increases power efficiency in power FET applications with varying loads. A constant frequency mode can be used without detracting from efficiency. This is accomplished by reducing repetitive gate charge power losses. The present invention controls the channel im |
| 6998907 |
Apparatus and method for receiving high-common mode voltage range signals with low-voltage devic |
February 14, 2006 |
| An input stage employs low-voltage MOSFETs as input devices for an operational amplifier circuit that operates at common mode voltages that may exceed the gate-oxide breakdown voltage of the input devices. Also, the input stage is arranged for relatively low noise. The input stage is |
| 6998830 |
Band-gap reference |
February 14, 2006 |
| A reference circuit includes a band-gap core, two current sources, and an amplifier circuit that are arranged in cooperation. The band-gap core circuit is biased by current that is supplied from a local power supply via the first current source. The second current source shunts the exces |
| 6998798 |
Digitally controlled vertical S linearity correction with constant amplitude without using an AG |
February 14, 2006 |
| A digitally-controlled vertical S linearity correction with a constant amplitude without using an AGC. To preserve line spacing between horizontal lines toward a top and bottom of a screen a third order correction voltage V.sub.cube is applied to a sweep voltage V.sub.osc. A constant |
| 6998782 |
Circuit for generating a process-independent current |
February 14, 2006 |
| Based, in part, on an input video signal, an autobias circuit generates red, green, and blue channel video signals, which are received by external drivers to drive cathodes in a CRT. The autobias circuit also provides gain and bias control signals based on a sense current. The extern |
| 6998651 |
LVTSCR-like structure with blocking junction under the polygate |
February 14, 2006 |
| In a LVTSCR-like structure, an additional p+ region is formed adjacent a n+ floating drain to define a p-n junction with the floating drain underneath a polygate of the structure. The polygate is used as a mask during doping of the p+ region and the n+ floating drain, and the length |
| 6995526 |
Digitally controlled vertical C linearity correction with constant start and end points without |
February 7, 2006 |
| A method and circuit for digitally controlled vertical C linearity correction with constant start and end points without using an AGC. A squared voltage and a negative squared voltage are added as a correction voltage to a sawtooth-shaped ramping voltage that is employed to sweep an |
| 6992927 |
Nonvolatile memory cell |
January 31, 2006 |
| An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation. |
| 6992512 |
Output buffer |
January 31, 2006 |
| The present invention is related an output buffer that has one input pin and produces a two-bit output. The input levels are a ground voltage, a supply voltage, and a voltage that is halfway between ground and supply. The invention is related to producing a minimal current when the input |
| 6990061 |
Method and apparatus for channel estimation |
January 24, 2006 |
| This invention relates to a method and apparatus for channel estimation. A method of determining a maximum likelihood frequency domain estimate of the channel response of a channel between at least one transmitting peer and at least one receiving peer, the method comprising transmitting |
