| Patent Number |
Title Of Patent |
Date Issued |
| 7088163 |
Circuit for multiplexing a tapped differential delay line to a single output |
August 8, 2006 |
| A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential delay stage and a |
| 7088146 |
Apparatus and method for high-speed half-latch with low overdrive voltage |
August 8, 2006 |
| A half-latch that includes negative feedback circuitry is provided. The negative feedback circuitry causes the steady-state gain of the half-latch to remain high so that the overdrive voltage needed to change the state of the half-latch is significantly reduced. Additionally, the neg |
| 7088139 |
Low power tri-level decoder circuit |
August 8, 2006 |
| A tri-level decoder circuit includes a first decoder circuit and a second decoder circuit. The first decoder circuit is configured to compare an input voltage to a first threshold, and the second decoder circuit is configured to compare the input voltage to a second threshold. The first |
| 7087986 |
Solder pad configuration for use in a micro-array integrated circuit package |
August 8, 2006 |
| A solder pad configuration for use in an IC package is described. Various embodiments of the invention describe IC packages, lead-frames, or substrate panels configured with generally noncircular solder pads at their bottom surfaces. The noncircular shapes allow for greater surface a |
| 7087979 |
Bipolar transistor with an ultra small self-aligned polysilicon emitter |
August 8, 2006 |
| The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer of epitaxial material |
| 7087978 |
Semiconductor resistor with improved width accuracy |
August 8, 2006 |
| The accuracy of the width measurement of a semiconductor resistor is improved by modifying the gate mask of a standard MOS transistor fabrication process to form an opening between regions of polysilicon that are used as a mask when the substrate or well material is implanted to form |
| 7087927 |
Semiconductor die with an editing structure |
August 8, 2006 |
| Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite |
| 7087503 |
Shallow self isolated doped implanted silicon process |
August 8, 2006 |
| A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of differen |
| 7086788 |
Optical sub-assembly for opto-electronic modules |
August 8, 2006 |
| Concepts for conveniently arranging devices for the transduction of signals to and from voltage and current domains to infrared radiation domains is described. Specifically, optoelectronic components and methods of making the same are described. In one aspect, the optoelectronic comp |
| 7086786 |
Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired |
August 8, 2006 |
| A high performance ceramic block for use with small-scale circuitry is described. The block can be used in an optical sub-assembly (OSA) suitable for optical interconnection with optical fibers and electrical interconnection with a chip sub-assembly (CSA) is formed. The block include |
| 7084670 |
Phase-frequency detector with gated reference clock input |
August 1, 2006 |
| A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency detector includes |
| 7082377 |
Apparatus for error cancellation for dual diode remote temperature sensors |
July 25, 2006 |
| A temperature measurement circuit for a dual junction temperature sensor is provided. The temperature measurement circuit is configured to provide separate bias currents to the junctions in the temperature sensor. The temperature measurement circuit includes two signal channels configure |
| 7082291 |
Automatic gain control |
July 25, 2006 |
| A method for controlling gain of an amplifier includes amplifying one or more received signals to produce one or more amplified signals. The method also includes generating a plurality of down converted signals using the one or more amplified signals. The method further includes ampl |
| 7081901 |
Display system with framestore and stochastic dithering |
July 25, 2006 |
| A display system provides stochastic dithering to image data for storage in a frame buffer for display. Dithering is used to reduce the size of the frame buffer and to reduce the complexity of the drive circuitry that is used to display an image. The bit depth of the frame buffer is redu |
| 7081663 |
Gate-enhanced junction varactor with gradual capacitance variation |
July 25, 2006 |
| A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling |
| 7079589 |
Serial digital communication superimposed on a digital signal over a single wire |
July 18, 2006 |
| A communications system interleaves control pulses between the transitions in a serial bit stream to form an interleaved signal. The serial bit stream has a series of transitions and a series of gaps between transitions where a transition can not occur. An interleaver identifies gaps |
| 7078787 |
Design and operation of gate-enhanced junction varactor with gradual capacitance variation |
July 18, 2006 |
| A semiconductor junction varactor is designed with gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for |
| 7075475 |
Correlated double sampling modulation system with reduced latency of reference to input |
July 11, 2006 |
| A charge balancing modulation system for digitizing the output of a variable impedance sensor utilizes synchronous excitation of the input sensor and AC coupling of the analog input signal. In one embodiment, the modulation system includes a switched excitation source for exciting the |
| 7075376 |
Frequency synthesizer using digital pre-distortion and method |
July 11, 2006 |
| A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by |
| 7075360 |
Super-PTAT current source |
July 11, 2006 |
| A super-PTAT current source receives a PTAT reference voltage as input. The PTAT reference voltage is combined with the gate-to-source voltage difference of two unequal-area input transistors and the combined voltage is imposed on a high negative temperature coefficient resistor to produ |
| 7075353 |
Clock generator circuit stabilized over temperature, process and power supply variations |
July 11, 2006 |
| A clock generator circuit incorporates a sub-PTAT (proportional to absolute temperature) current source and a super-PTAT current source for generating bias currents for a voltage reference generator and charging currents for a voltage ramp generator. The clock generator circuit furth |
| 7075346 |
Synchronized frequency multiplier for multiple phase PWM control switching regulator without usi |
July 11, 2006 |
| A method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A period of the input clock signal is measured by using a frequency |
| 7075341 |
Low area linear time-driver circuit |
July 11, 2006 |
| A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode. |
| 7075133 |
Semiconductor die with heat and electrical pipes |
July 11, 2006 |
| Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top |
| 7073961 |
Optical sub-assembly packaging techniques that incorporate optical lenses |
July 11, 2006 |
| Techniques for manufacturing an optical transmission device in a manner so that the photonic device is protected from damage that can be caused by exposure to the environment and physical handling are described. The invention involves placing a lens or a lens array over a photonic device |
| 7073077 |
Apparatus for cutting power to processing circuitry in a network interface |
July 4, 2006 |
| A network interface that consumes no power when it is not connected to an external network. The network interface comprises: i) a data transceiver for transmitting data to and receiving data from an external network coupled to the network interface; ii) a connection jack into which a |
| 7071969 |
Parameterized preview array for iterative image optimization in remote applications |
July 4, 2006 |
| A method of adjusting focus and/or other image parameters in a remotely-operated image capturing system, such as a scanning electron microscope (SEM), is provided. The method minimizes transmission bandwidth and allows a remote user to perform adjustment quickly without requiring rea |
| 7071764 |
Back-drive circuit protection for I/O cells using CMOS process |
July 4, 2006 |
| In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at subst |
| 7071761 |
Apparatus and method for reducing propagation delay |
July 4, 2006 |
| A timer circuit is arranged for reduced propagation delay and improved stability at low supply voltages. The timer circuit includes a capacitor circuit, a voltage offset circuit, an inverter circuit, and a current source circuit. The current source circuit is arranged to provide a cu |
| 7071739 |
Termination sense-and-match differential driver |
July 4, 2006 |
| A differential driver circuit is configured to automatically adjust its source resistance to be substantially similar to a termination resistance. The differential driver circuit includes a variable resistance circuit on each leg of the differential driver circuit. A replica of one l |
| 7071670 |
Generating reference voltages |
July 4, 2006 |
| A reference voltage is generated between a first node and a second node. A resistive element and a junction device are coupled in series between the first node and the second node. The junction device includes a junction between dissimilar materials, and has a negative temperature coeffi |
| 7071630 |
Closed loop magnetic boost LED driver system and method |
July 4, 2006 |
| Current is delivered to a load using a closed-loop boost circuit topology that is suitable for LED driver applications. An inductor is charged when a transistor is active during a first operating phase. The inductor delivers current to the load when the transistor is inactive during a |
| 7071513 |
Layout optimization of integrated trench VDMOS arrays |
July 4, 2006 |
| An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low R.sub.ds(on) area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and d |
| 7069461 |
Closed-loop, supply-adjusted RAM memory circuit |
June 27, 2006 |
| The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes fro |
| 7068195 |
Accurate sampling technique for ADC |
June 27, 2006 |
| A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more contro |
| 7068194 |
High-density MOS-decoded unary DAC |
June 27, 2006 |
| Multiple switching circuits and current source circuits are arranged to operate as part of a compact unary DAC cell. The compact unary DAC cell can be combined with additional compact unary DAC cells to provide a scalable unary DAC system that may be segmented, non-segmented, single- |
| 7068098 |
Slew rate enhancement circuit |
June 27, 2006 |
| An operational amplifier (op-amp) (200, 800, 900) having at least a first stage and a second stage has a feedback path (825) from the output to the input of a second stage, the feedback path includes a first capacitor (801) and a second capacitor (803) in series connected at a node (815) |
| 7067927 |
Die with integral pedestal having insulated walls |
June 27, 2006 |
| A variety of techniques and structures are described that integrate an insulated pedestal into the back surface of integrated circuit dice. The die has an insulated integral pedestal formed therein that acts as a spacer. The pedestal has a footprint that is smaller than the total foo |
| 7067879 |
Integration of trench power transistors into a 1.5 .mu.m BCD process |
June 27, 2006 |
| The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra |
| 7067852 |
Electrostatic discharge (ESD) protection structure |
June 27, 2006 |
| An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are |
| 7067384 |
Method of forming a varactor with an increased linear tuning range |
June 27, 2006 |
| The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plat |
| 7067354 |
Electrical die contact structure and fabrication method |
June 27, 2006 |
| A semiconductor device of the invention includes an integrated circuit formed on a semiconductor substrate having first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semic |
| 7065424 |
Systems and methods that monitor re-qualification indicia associated with durable items to ensur |
June 20, 2006 |
| This invention introduces systems and methods that control production process quality, wherein the production process has a plurality of durable items, each durable item is associated with a re-qualification process initiated as a function of a life expectancy associated therewith. T |
| 7065133 |
Receiver architecture using mixed analog and digital signal processing and method of operation |
June 20, 2006 |
| There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction |
| 7064599 |
Apparatus and method for signal transmission |
June 20, 2006 |
| A signal transmission gate includes a switch such as a transistor. The switch includes a gate terminal adapted to receive a control voltage, and a source terminal and a drain terminal. One of the source and drain terminals is adapted to receive an input signal, and the output signal is |
| 7064492 |
Automatic ambient light compensation for display backlighting |
June 20, 2006 |
| Control circuitry is used to control the backlighting of electronic displays. A light sensor (such as a phototransistor) is used to continuously measure ambient light conditions that are associated with an electronic display. A linear, continuous light-level signal is produced in res |
| 7064419 |
Die attach region for use in a micro-array integrated circuit package |
June 20, 2006 |
| A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during |
| 7064397 |
Silicon controlled rectifier structure with improved punch through resistance |
June 20, 2006 |
| When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantia |
| 7062769 |
Object-oriented processor design and design methodologies |
June 13, 2006 |
| A distributed processing system having a host processor including a host communication infrastructure (HCI) configured for communication with said host processor; a plurality of class processors each having an associated private localized read/write memory; and a plurality of application |
| 7062666 |
Signal-initiated method for suspending operation of a pipelined data processor |
June 13, 2006 |
| A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal. |
