| Patent Number |
Title Of Patent |
Date Issued |
| 7116734 |
Method and system for providing maximum likelihood detection with decision feedback interference |
October 3, 2006 |
| A method for providing maximum likelihood detection with decision feedback interference cancellation is provided. The method includes estimating a current symbol with previous symbol interference (PSI) removed based on estimated previous symbols. A next symbol is estimated with PSI remov |
| 7115973 |
Dual-sided semiconductor device with a resistive element that requires little silicon surface ar |
October 3, 2006 |
| A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon s |
| 7115951 |
Low triggering voltage ESD protection structure and method for reducing the triggering voltage |
October 3, 2006 |
| In a triggering ESD protection structure, the triggering voltage is reduced by introducing one or more corners or spikes into the p-n breakdown junction. This may be done by providing a polygate with a zig-zag pattern to define triangular corners in the drain or anode of the structur |
| 7115500 |
System and method for providing a dry-wet-dry etch procedure to create a sidewall profile of a v |
October 3, 2006 |
| A system and method is disclosed for providing a dry-wet-dry etch procedure to create a sidewall profile of a via in a semiconductor device. A first vertical anisotropic dry etch process is applied to etch through a first portion of a dielectric layer. An isotropic wet etch process i |
| 7114908 |
Method and apparatus for stacking semiconductor wafers |
October 3, 2006 |
| An apparatus for stacking semiconductor wafers comprises a housing configured to releasably maintain a plurality of semiconductor wafers in fixed positions relative to the housing. The apparatus also includes a transfer guide proximate to the housing, the transfer guide configured to |
| 7113969 |
Formatting denormal numbers for processing in a pipelined floating point unit |
September 26, 2006 |
| A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an |
| 7113427 |
NVM PMOS-cell with one erased and two programmed states |
September 26, 2006 |
| NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two |
| 7113050 |
Integrated circuit with oscillator and electrostatic discharge protection |
September 26, 2006 |
| An integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection in which the parasitic capacitance of the ESD protection circuitry is disassociated from the oscillator circuitry to minimize loading of the tank circuit thereby minimizing degradation of the tank |
| 7113014 |
Pulse width modulator |
September 26, 2006 |
| A low-power, synchronous pulse width modulator utilizes a first clock signal at a first frequency to generate a pulse-width modulated signal at the first frequency without requiring a second over sampling clock signal that has a substantially higher frequency by selecting taps from a pha |
| 7112981 |
Method of debugging a 3D packaged IC |
September 26, 2006 |
| In a method of testing a 3D packaged IC, the dies are tested under power by mounting on a specifically designed printed circuit board with a window in it for testing the die sequentially from below using a laser beam tester. The die found not to be defective is partially removed in s |
| 7110729 |
Apparatus and method for generating a temperature insensitive reference current |
September 19, 2006 |
| A constant current source for generating a constant reference current that is relatively temperature insensitive. The constant current source comprises: i) first circuitry for generating a first output current that increases with increases in temperature; ii) second circuitry for gen |
| 7109747 |
Low power, high speed logic controller that implements thermometer-type control logic by utilizi |
September 19, 2006 |
| The power dissipation, logic complexity and chip area of a thermometer controller are all significantly reduced by utilizing a series of scan flip-flops that are connected together to form a bi-directional shift register, along with a gated clock signal that clocks the series of scan |
| 7109688 |
Apparatus and method for monotonic start up of a synchronous switching regulator |
September 19, 2006 |
| A controller for a synchronous switching regulator is arranged to control a switch with a control signal, and to control a synchronous switch with a synchronous switch control signal. The controller disables the synchronous switch control signal at power-up so that the regulator oper |
| 7109587 |
Apparatus and method for enhanced thermal conductivity packages for high powered semiconductor d |
September 19, 2006 |
| An apparatus and method for an enhanced thermally conductive package for high powered semiconductor devices. The package includes a semiconductor die having an active surface and a non-active surface and a metal layer formed on the non-active surface of the die. The package is intended t |
| 7109571 |
Method of forming a hermetic seal for silicon die with metal feed through structure |
September 19, 2006 |
| A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconduct |
| 7107380 |
Configuration for dockable portable computers using a single ethernet physical layer chip and tr |
September 12, 2006 |
| A single 10/100/1000BT Ethernet network physical layer chip and a single transformer, both within a mobile computer, are employed to provide a network connection to the mobile computer either through a network connection interface within a docking station receiving the mobile compute |
| 7106040 |
Adaptive voltage scaling power supply for use in a digital processing component and method of op |
September 12, 2006 |
| There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; |
| 7106038 |
Increased output range and decreased gain variation PWM circuit and method |
September 12, 2006 |
| A pulse-width modulator (PWM) accommodates a wider range of output pulse widths, with less gain variation, when compared to conventional circuits. The PWM can operate without requiring a voltage reference. In one example PWM, a ramp generator in the PWM includes a capacitive element that |
| 7106036 |
Apparatus and method for high-frequency PWM with soft-start |
September 12, 2006 |
| A boost regulator circuit with soft-start is arranged for high-frequency pulse width modulation of LED current. When a shutdown signal is asserted, all circuitry in the boost regulator circuit is disabled, except for circuitry needed for a shutdown delay timer. Also, when the shutdow |
| 7105906 |
Photodiode that reduces the effects of surface recombination sites |
September 12, 2006 |
| The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination sites, and a seco |
| 7105373 |
Vertical photodiode with heavily-doped regions of alternating conductivity types |
September 12, 2006 |
| A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a |
| 7103334 |
Method and system for tuning quality factor in high-Q, high-frequency filters |
September 5, 2006 |
| A method for tuning quality factor (Q) in a high-Q, high-frequency filter is provided that includes filtering an input signal to generate a filtered signal. The input signal comprises a specified frequency. The filtered signal comprises an actual phase shift with respect to the input |
| 7102703 |
Liquid crystal display assembly for reducing optical defects |
September 5, 2006 |
| An improved packaged liquid crystal display (LCD) assembly is described. A recess is used to house a support material while the LCD cell 609 is positioned at least partially within the containment structure. A plurality of spaced apart stabilizers are attached from the sides of the L |
| 7102613 |
Low cost vertical visual indicator system for on screen displays |
September 5, 2006 |
| A circuit has been shown to illustrate how a vertical indicator can be generated in logic for a simplified OSD generator. The vertical visual indicator generated uses little microcontroller firmware overhead allowing a less powerful microcontroller to be used in the specific applicat |
| 7102610 |
Display system with frame buffer and power saving sequence |
September 5, 2006 |
| A method is arranged to process a frame for an LCD with a modified polarity pattern. The pattern employs a polarity reversal scheme that results in line inversion and/or dot inversion patterns that are observable by pixel locations within the frame. The drive polarity for the column |
| 7102415 |
Trip-point detection circuit |
September 5, 2006 |
| A current is provided from a power source to a load through a pass circuit that is series coupled to a sense resistor. A current trip-point detection circuit is arranged to detect a change in the current that is provided to a load. The current trip-point detection circuit includes at |
| 7102398 |
Circuit for two PLLs for horizontal deflection |
September 5, 2006 |
| A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL |
| 7102371 |
Bilevel probe |
September 5, 2006 |
| An apparatus for electrical testing of semiconductor devices is provided. A printed circuit board is provided. A first plurality of probe pins for probing bump connectors is electrically and mechanically connected to the printed circuit board. A second plurality of probe pins for probing |
| 7102209 |
Substrate for use in semiconductor manufacturing and method of making same |
September 5, 2006 |
| A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to fo |
| 7101787 |
System and method for minimizing increases in via resistance by applying a nitrogen plasma after |
September 5, 2006 |
| A system and method is disclosed for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition. A via in a semiconductor device is formed by placing a metal layer on a substrate and placing a layer of anti-reflective coating (ARC) titanium |
| 7101620 |
Thermal release wafer mount tape with B-stage adhesive |
September 5, 2006 |
| In one aspect, an improved wafer mount tape is provided. The wafer mount tape includes a base layer, a release layer that expands when activated and a B-stageable adhesive layer that is positioned over the release layer. In a method aspect of the invention, a wafer level method of pl |
| 7099536 |
Single lens system integrating both transmissive and reflective surfaces for light focusing to a |
August 29, 2006 |
| An integrated lens and mirror assembly for use in a fiber optic transmitter optical sub-assembly is disclosed. The lenses fabricated from a single monolithic block of optically transparent material. One region of the lens assembly is configured to transmit and focus light signals. A |
| 7098751 |
Tunable capacitance circuit for voltage control oscillator |
August 29, 2006 |
| A circuit and method for providing a tunable capacitance for a voltage control oscillator (VCO) in which at least one P-N junction varactor and at least one metal oxide semiconductor (MOS) accumulation-mode varactor are effectively coupled and tuned in parallel, thereby providing a net |
| 7098728 |
Output voltage correction circuit for multiplexed multi-phase hysteretic voltage regulator |
August 29, 2006 |
| A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is |
| 7098720 |
High impedance thermal shutdown circuit |
August 29, 2006 |
| A thermal shutdown circuit board integrated circuit device. The thermal shutdown circuit includes a current source for receiving a current bias and generating an output current in accordance therewith. The current source is configured to produce the output current in a manner proport |
| 7098706 |
High speed synchronizer for simultaneously initializing rising edge triggered and falling edge t |
August 29, 2006 |
| The rising edge triggered flip-flops and falling edge triggered flip-flops in one or more clock domains of a target system can be simultaneously initialized to predetermined logic states by activating the flip-flop set/clear inputs, freezing the flip-flop clock signals high or low, s |
| 7098540 |
Electrical interconnect with minimal parasitic capacitance |
August 29, 2006 |
| The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds |
| 7098518 |
Die-level opto-electronic device and method of making same |
August 29, 2006 |
| In one embodiment of the invention, a die-level opto-electronic device comprises a semiconductor die having edges and a photonic device exposed on a first surface. The device includes a conductive structure formed in the die and away from the edges of the die, the conductive structure |
| 7098095 |
Method of forming a MOS transistor with a layer of silicon germanium carbon |
August 29, 2006 |
| The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and dra |
| 7098044 |
Method of forming an etched metal trace with reduced RF impedance resulting from the skin effect |
August 29, 2006 |
| The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q. |
| 7096133 |
Method of establishing benchmark for figure of merit indicative of amplifier flicker noise |
August 22, 2006 |
| A method of establishing a benchmark for a figure of merit indicative of flicker noise of an amplifier circuit. |
| 7095811 |
Apparatus and method for secondary synchronization channel detection in a 3GPP WCDMA receiver |
August 22, 2006 |
| A pipelined cell search apparatus comprises a secondary search stage that receives a secondary synchronization channel (S-SCH) signal. The secondary search stage comprises: 1) a correlation block for i) correlating the S-SCH signal with a 256-bit sequence z to produce a first correla |
| 7095407 |
Method and apparatus for reducing noise in a graphics display system |
August 22, 2006 |
| The present invention is related to staggering data to reduce noise in a graphics display system. Line-to-line data staggering is achieved by staggering the starting point at which data is transmitted within each line of data. Frame-to-frame staggering is implemented by staggering the |
| 7095116 |
Aluminum-free under bump metallization structure |
August 22, 2006 |
| An apparatus and method for providing aluminum free under bump metallization stacks in an integrated circuit device is disclosed. Included is the use of vias having substantially non-vertical sidewalls that are formed in a resilient layer, such as benzocyclobutene. In general, semico |
| 7095096 |
Microarray lead frame |
August 22, 2006 |
| Processes for packaging integrated circuits in microarray packages are described. In a method aspect of the invention, a first side of a metal sheet is etched to define a lead frame panel having a plurality of device areas. Each device area includes an array of contact posts suitable for |
| 7093054 |
Method of transferring signals between a TTL microcontroller and a RS232 device |
August 15, 2006 |
| A switching transistor is placed between a serial port of a RS232 device and a parallel port of a TTL microcontroller. Selective activation of the switching transistor permits a high voltage signal to be transmitted from the power supply rail of the TTL microcontroller to the RXD pin of |
| 7092475 |
Phase-frequency detector with linear phase error gain near and during phase-lock in delta sigma |
August 15, 2006 |
| A phase-frequency detector (PFD) having substantially linear phase error gain within a predetermined phase error range centered about zero phase error when used in a delta sigma phase-locked loop (PLL). The output signals (e.g., charge pump control signals), which are also used to reset |
| 7089339 |
Sharing of functions between an embedded controller and a host processor |
August 8, 2006 |
| An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more |
| 7089146 |
Apparatus and method for sub-ranging conversion for temperature sensing |
August 8, 2006 |
| A circuit for temperature sensing receives a differential voltage that corresponds to the voltage across a forward-biased PN junction. The circuit for temperature sensing provides a first current to the PN junction, and subsequently provides a second current. Also, the temperature of |
| 7088281 |
Coarse channel calibration for folding ADC architectures |
August 8, 2006 |
| A circuit for calibrating a coarse channel circuit in a folding analog-to-digital converter circuit. A reference value is input to the coarse channel circuit and an output of the coarse channel circuit is sensed. A parameter of the coarse channel circuit is adjusted until the coarse |
