| Patent Number |
Title Of Patent |
Date Issued |
| 7158139 |
Simple on screen display system using mapped ROM generated characters |
January 2, 2007 |
| The present invention provides a low cost OSD system with minimal ROM requirements, minimal computing power required from the microcontroller, and minimal I/O port requirements. The OSD system creates a fixed frame around a small set of programmable characters. The small set of progr |
| 7157891 |
DC-DC voltage converter with reduced output voltage ripple |
January 2, 2007 |
| An integrated DC--DC converter circuit in which multiple switched circuits operate in parallel to drive the output electrode with multiple pulsed charging voltages such that the corresponding respective output ripple voltage components combine with destructive interference, thereby r |
| 7156562 |
Opto-electronic module form factor having adjustable optical plane height |
January 2, 2007 |
| An apparatus opto-electronic module that is flexible in design such that components of different types and dimensions can be incorporated into the module without straying from certain mechanical standards requirements is described. Generally, an opto-electronic module of the present inve |
| 7151442 |
System, apparatus, and method for testing identification tags |
December 19, 2006 |
| An apparatus includes at least one tag holder capable of receiving and holding a plurality of tags. The apparatus also includes at least one antenna capable of receiving wireless signals from the plurality of tags during a test of the tags. The apparatus may further include at least one |
| 7150561 |
Zero temperature coefficient (TC) current source for diode measurement |
December 19, 2006 |
| A method and circuit for reducing a temperature dependent error in p-n junction based temperature measurements. The temperature-dependent error may be caused by parasitic resistance in a p-n junction and temperature dependent variation of a bias current in a temperature sensor. A dif |
| 7149903 |
System and method for signal delay in an adaptive voltage scaling slack detector |
December 12, 2006 |
| A system and method for slack determination in a logic integrated circuit. A launch pulse is input to a circular delay loop circuit. The leading edge of the launch pulse causes a pulse to circulate around the circular delay loop. The number of passes made through the loop by the circulat |
| 7148757 |
Charge pump-based PLL having dynamic loop gain |
December 12, 2006 |
| A charge pump-based PLL dynamically controls loop gain in response to the frequency of an input signal. The loop gain is dynamically adjusted by varying the bias current of the charge pump circuit of the PLL. The bias current is varied in response to the voltage of a loop filter that is |
| 7148668 |
Completely isolated synchronous boost DC-to-DC switching regulator |
December 12, 2006 |
| The leakage current due to a parasitic PNP bipolar transistor in the PMOS switching transistor of a synchronous boost DC-to-DC switching regulator is substantially eliminated by placing the input voltage on the body of the PMOS switching transistor when the input voltage is greater than |
| 7145191 |
P-channel field-effect transistor with reduced junction capacitance |
December 5, 2006 |
| The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a |
| 7145187 |
Substrate independent multiple input bi-directional ESD protection structure |
December 5, 2006 |
| In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs a |
| 7144800 |
Multichip packages with exposed dice |
December 5, 2006 |
| Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher |
| 7144795 |
Method for forming a depletion-mode transistor that eliminates the need to separately set the th |
December 5, 2006 |
| A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity |
| 7142222 |
Halftone controller circuitry for video signal during on-screen-display (OSD) window |
November 28, 2006 |
| Digital circuitry for imparting halftone to that portion of a video image over which an on-screen-display (OSD) window is superimposed. |
| 7142042 |
Nulled error amplifier |
November 28, 2006 |
| A multi-stage amplifier circuit that is arranged to minimize offset related errors in a reference circuit. The first stage circuit includes an array of amplifier circuits that receive feedback signals. The outputs of the first stage amplifier circuits are coupled together to a common |
| 7141955 |
Apparatus and method for monitoring current for a high-side switch |
November 28, 2006 |
| A switching buck regulator circuit includes an n-type high-side switch. The driver of the high-side switch employs a boot voltage (Vcboot) as a power supply. Also, the output current is mirrored to a sense branch. A current sense voltage is generated employing a transistor in the sense |
| 7141831 |
Snapback clamp having low triggering voltage for ESD protection |
November 28, 2006 |
| An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of |
| 7139342 |
System and method for cancelling signal echoes in a full-duplex transceiver front end |
November 21, 2006 |
| There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo cancell |
| 7139322 |
Method for reducing peak-to-average power ratios in a multi-carrier transmission system |
November 21, 2006 |
| The present invention provides a technique to reduce peak-to-average power ratio (PAR) of multi-carrier transmission systems. A non-empty subset of the subcarriers includes "PAR subcarriers." The PAR subcarriers have constellations obtained by reducing a constellation that is higher than |
| 7137089 |
Systems and methods for reducing IR-drop noise |
November 14, 2006 |
| The diffusion structures in CMOS devices can be changed to minimize the effects of IR drop on those devices. A simulation can be run before tape-off to determine which transistors are at risk. The area of the source region and/or the width of the drain region of the at-risk transisto |
| 7136000 |
Selective offset adjustment of a track and hold circuit |
November 14, 2006 |
| A track/hold circuit with an offset adjustment that can be used to compensate for offset errors from other parts of the system containing the track/hold circuit. The offset adjustment may be provided by impressing a voltage at an electrode of a capacitor of the track/hold circuit dur |
| 7135902 |
Differential signal generator having controlled signal rise and fall times with built-in test ci |
November 14, 2006 |
| Integrated differential data signal generator circuitry for providing differential data signals with controlled rise and fall times and built-in test capabilities. |
| 7135894 |
Dual-output current driver |
November 14, 2006 |
| A dual-output current driver includes a pair of output stages that provide output current to various devices such as LEDs and laser diodes. An output-stage selector circuit that includes a differential pair is arranged to activate one of the output stages at a time. A pair of push-pu |
| 7135841 |
Emulated inductor current automatic correction without knowledge of actual inductor current ramp |
November 14, 2006 |
| Method and circuit for automatic correction of emulated inductor current without knowledge of actual inductor current ramp for an emulated current mode (ECM) PWM switching regulator. In an ECM-PWM switching regulator a compensation ramp component is usually added to an up-slope. An exces |
| 7135385 |
Semiconductor devices having a back surface protective coating |
November 14, 2006 |
| A wafer level method of forming a protective coating on the back surface of integrated circuit devices is described. In one aspect, a tape having a backcoat layer and a mount layer is applied to the back surface of a wafer. The backcoat layer is cured or set such that the backcoat layer |
| 7133483 |
Apparatus and method for a jitter cancellation circuit |
November 7, 2006 |
| The invention produces an output signal that maintains a substantially constant period corresponding to a clock signal. An input signal includes a period that is an integer multiple of the period of the clock signal. The timing or phase of the input signal may shift in comparison to the |
| 7132887 |
Low voltage semi-folded metal oxide semiconductor field effect transistor (MOSFET) amplifier cir |
November 7, 2006 |
| A low voltage semi-folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dime |
| 7132344 |
Super self-aligned BJT with base shorted field plate and method of fabricating |
November 7, 2006 |
| A bipolar junction transistor (BJT) structure and fabrication method are provided in which a doped polysilicon filled trench is utilized to form both the extrinsic base contact region and a vertical field plate. A sacrificial mandrel of dielectric material is formed over regions that |
| 7132342 |
Method of reducing fringing capacitance in a MOSFET |
November 7, 2006 |
| In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers. |
| 7130693 |
Method for increasing the resolution and decreasing the power dissipation in eye prosthetics |
October 31, 2006 |
| A method for increasing a resolution and decreasing a power dissipation in an epiretinal implant device is described. The method includes positioning extendable microprobes to achieve mechanical contact with an anterior surface of the retina when the epiretinal implant device is acti |
| 7130604 |
Harmonic rejection mixer and method of operation |
October 31, 2006 |
| A radio frequency (RF) demodulation circuit comprising a harmonic rejection mixing stage capable of receiving and mixing an incoming radio frequency (RF) signal having a frequency RF and a reference local oscillator (LO) signal having a frequency LO and generating an output signal in |
| 7129686 |
Apparatus and method for a high PSRR LDO regulator |
October 31, 2006 |
| A tail current source is provided. The tail current source may be used in amplifiers, in an error amplifier of an LDO, or the like, to achieve high PSRR. The tail current source includes a first current mirror, a capacitor, a resistive device, and a current mirror circuit. The current |
| 7127718 |
Multitasking microcontroller for controlling the physical layer of a network interface card and |
October 24, 2006 |
| There is disclosed an apparatus for controlling a physical layer interface of a network interface card in real time. The apparatus comprises: 1) a first memory for storing a multitasking control program, the multitasking control program comprising a main routine and a plurality of subrou |
| 7126866 |
Low power ROM architecture |
October 24, 2006 |
| In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the |
| 7126397 |
Pulse width modulation carrier frequency technique |
October 24, 2006 |
| A PWM method and circuit. A temporary PWM signal is generated at a first frequency. The temporary PWM signal includes analog duty cycle information adapted for the first frequency. At least a portion of the analog duty cycle information is converted to digital duty cycle information |
| 7126396 |
System for clock duty cycle stabilization |
October 24, 2006 |
| A clock signal duty cycle stabilization system. The system includes a clock signal duty cycle stabilization circuit having an edge detection circuit and a latch circuit. The edge detection circuit is configured to receive an external clock signal and generate an output therefrom. The |
| 7126316 |
Difference amplifier for regulating voltage |
October 24, 2006 |
| A voltage regulation circuit. The voltage regulator includes an input stage, a reference voltage circuit, a gain stage, and an output stage. The reference voltage circuit is coupled to one input of the input stage, and the output stage is coupled to another input of the input stage. The |
| 7126168 |
Silicon controlled rectifier structures with reduced turn on times |
October 24, 2006 |
| The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn trans |
| 7123179 |
Apparatus and method for duty cycle conversion |
October 17, 2006 |
| A reference signal generator for generating an output reference signal having a target duty cycle. The reference signal generator comprises a sawtooth generator for receiving an input reference signal having a reference frequency and generating a sawtooth waveform having the referenc |
| 7123170 |
System and method for a data-input array capable of being scanned using a reduced number of sign |
October 17, 2006 |
| A system and method for scanning a data-input array (e.g., a keyboard or keypad) using a reduced number of signals is disclosed. Specifically, a switch array is disclosed comprising a plurality of switches and a plurality of input/output (I/O) lines. The switch array is arranged in an |
| 7123053 |
Circuitry for providing overvoltage backdrive protection |
October 17, 2006 |
| A logic gate for use in an electronic system comprising: i) a first component operating from a low voltage power supply rail; ii) a second component operating from a high voltage power supply rail; and iii) an over-voltage protection circuit that detects an over-voltage on an output |
| 7122996 |
Voltage regulator circuit |
October 17, 2006 |
| A voltage regulator circuit is arranged to provide a regulated output voltage from an unregulated input voltage. Also, the voltage regulator circuit includes a capacitor that is coupled between output and feedback nodes of the voltage regulator circuit. The capacitor may improve tran |
| 7121146 |
MEMS pressure sensing device |
October 17, 2006 |
| A pressure sensing system formed in a monolithic semiconductor substrate. The pressure sensing system comprises a pressure sensing device formed on the monolithic semiconductor substrate. Pressure sensing device is adapted to be disposed in an environment for developing an electrical |
| 7120810 |
Instruction-initiated power management method for a pipelined data processor |
October 10, 2006 |
| An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry. |
| 7119612 |
Dual-channel instrumentation amplifier |
October 10, 2006 |
| A dual-channel instrumentation amplifier includes two channels of PMOS transistor differential pairs which are configured in a Y-connection and cross-coupled to two diode-connected NMOS transistors. Each input channel has a non-linear voltage-current characteristic. But when the diff |
| 7119522 |
Apparatus and method for step-down switching voltage regulation |
October 10, 2006 |
| A current mode PWM buck regulator is provided. The regulator includes a top-side transistor, a bottom-side transistor, an inductor, a sample-and-hold circuit, a ramp generator, a PWM comparator, an error amplifier, and a current sense amplifier. A current through the low-side transis |
| 7119448 |
Main power inductance based on bond wires for a switching power converter |
October 10, 2006 |
| A method for providing main power inductance to a switching power supply using bond wires of an integrated circuit packaging. A predetermined number of bond wires are connected serially between standalone die bond pads and no-connect pins of the packaging. An output of the switching |
| 7119431 |
Apparatus and method for forming heat sinks on silicon on insulator wafers |
October 10, 2006 |
| An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat |
| 7118998 |
Method of forming a conductive structure |
October 10, 2006 |
| A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the |
| 7118973 |
Method of forming a transistor with a channel region in a layer of composite material |
October 10, 2006 |
| The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming |
| 7117378 |
Adaptive voltage scaling digital processing component and method of operating the same |
October 3, 2006 |
| There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a c |
