| Patent Number |
Title Of Patent |
Date Issued |
| 7192853 |
Method of improving the breakdown voltage of a diffused semiconductor junction |
March 20, 2007 |
| A method is provided for forming a graded junction in a semiconductor material having a first conductivity type. Dopant having a second conductivity type opposite the first conductivity type is introduced into a selected region of the semiconductor material to define a primary dopant |
| 7192819 |
Semiconductor sensor device using MEMS technology |
March 20, 2007 |
| A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming t |
| 7189645 |
System and method for adjusting the ratio of deposition times to optimize via density and via fi |
March 13, 2007 |
| A system and method is disclosed for adjusting the ratio of deposition times to optimize via density and via fill in an aluminum multilayer metallization process during a manufacturing process of a semiconductor wafer. In a two-step cold/hot aluminum sputtering process via fill becom |
| 7188044 |
World-wide distributed testing for integrated circuits |
March 6, 2007 |
| An integrated circuit test method is provided that utilizes shared tester resources physically located at different geographical sites throughout the world to test specific integrated circuits, thereby maximizing utilization of all tester resources and, thereby, dramatically reducing |
| 7187318 |
Pipeline ADC using multiplying DAC and analog delay circuits |
March 6, 2007 |
| Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay |
| 7187212 |
System and method for providing a fast turn on bias circuit for current mode logic transmitters |
March 6, 2007 |
| A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle "power down" state to an active "power up" state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias trans |
| 7187075 |
Stress relieving film for semiconductor packages |
March 6, 2007 |
| Techniques for reducing the mechanical stress imposed upon semiconductor dice by protective molding compounds during times of temperature fluctuation. A thermoplastic material is attached to a top surface of a die to relieve the stress. The thermoplastic material serves as a cushion |
| 7186588 |
Method of fabricating a micro-array integrated circuit package |
March 6, 2007 |
| A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder con |
| 7185042 |
High speed, universal polarity full adder which consumes minimal power and minimal area |
February 27, 2007 |
| A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal |
| 7184850 |
System and method for allocating multi-function resources for a wetdeck process in semiconductor |
February 27, 2007 |
| A system and method is disclosed for allocating multi-function resources among a plurality of tasks within a wetdeck process in semiconductor wafer fabrication. A resource allocator allocates multi-function resources among tasks within a process system that executes at least one appl |
| 7184798 |
Power conservation system and method |
February 27, 2007 |
| A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to po |
| 7184450 |
System and method for decoding audio/video data such as DVD or/and DVB data |
February 27, 2007 |
| A system (20) for decoding a data stream allocated into data packets contains a control unit (54), a stream demultiplexer (26), audio and video decoders (38 and 40), a memory management unit (60), and audio and video input and output buffers. Upon demultiplexing and depacketizing the |
| 7184099 |
Controllable signal baseline and frequency emphasis circuit |
February 27, 2007 |
| A circuit for selectively controlling signal baseline and frequency emphasis. An amplifier with selectively controllable feedback circuitry allows higher frequency components of a signal to be emphasized over lower frequency components while also allowing control over the baseline of |
| 7181835 |
Universal clamping mechanism |
February 27, 2007 |
| A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface o |
| 7181557 |
Single wire bus for connecting devices and methods of operating the same |
February 20, 2007 |
| A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the |
| 7180491 |
Application and method for rejection of a false data enable signal during vertical blanking peri |
February 20, 2007 |
| A false DE rejection system is described. DEs are ignored during a programmable vertical lockout period. Internal timing is used during the vertical lockout period to count the number of vertical lines to ignore. The first DE received after the vertical lockout period signifies the s |
| 7180379 |
Laser powered clock circuit with a substantially reduced clock skew |
February 20, 2007 |
| A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents |
| 7180140 |
PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk |
February 20, 2007 |
| A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum |
| 7180133 |
Method and structure for addressing hot carrier degradation in high voltage devices |
February 20, 2007 |
| In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including |
| 7178091 |
Reed solomon encoder |
February 13, 2007 |
| An Reed-Solomon encoder and method for block-code encoding by performing a plurality of Galois-Field (GF) multiplication operations utilizing a single GF multiplier. The multiplier generates a set of partial products that are used to calculate all the multiplication operations required f |
| 7177609 |
Chopper-direct-conversion (CDC) radio architecture |
February 13, 2007 |
| A chopper-direct-conversion (CDC) radio receiver includes a phase-alternating mixer receiving an antenna input signal and at least one local oscillator signal and generating a double sideband signal in a single mixing step. The phase-alternating mixer may be implemented by two parall |
| 7176929 |
Low cost animated sequence function for low cost OSD devices |
February 13, 2007 |
| The present invention provides a low cost animation sequence function for OSDs. An animation sequence is produced by changing the attributes associated with a character within the OSD rather than by substituting the character itself. A character may have several different attributes |
| 7176664 |
Method and system for providing precise current regulation and limitation for a power supply |
February 13, 2007 |
| A method for providing precise current regulation and limitation for a power supply is provided. The method includes amplifying any difference between a load current signal and a current setting reference signal with a feedback loop amplifier to generate a feedback signal. A power output |
| 7176530 |
Configuration and fabrication of semiconductor structure having n-channel channel-junction field |
February 13, 2007 |
| A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor ("IGFET") (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gat |
| 7175777 |
Method of forming a sub-micron tip feature |
February 13, 2007 |
| A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the |
| 7173741 |
System and method for handling bad pixels in image sensors |
February 6, 2007 |
| A method and apparatus for handling bad pixels in an image sensor array includes processing data values associated with the pixels of the image sensor. Processing the data values is performed by at least a first pass process and a subsequent pass process. In the first pass, the data valu |
| 7172977 |
Method for non-destructive removal of cured epoxy from wafer backside |
February 6, 2007 |
| Disclosed is a method for non-destructive removal of cured epoxy from a wafer backside. A wafer back-coated with epoxy is soaked in an acetone bath for a period of time, allowing degradation of the epoxy coating adhesion strength. The epoxy coating is then peeled or scraped away, lea |
| 7172973 |
System and method for selectively modifying a wet etch rate in a large area |
February 6, 2007 |
| A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a |
| 7171745 |
Apparatus and method for force mounting semiconductor packages to printed circuit boards |
February 6, 2007 |
| An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted o |
| 7171551 |
Serial interface for reprogramming multiple network interface cards and method of operation |
January 30, 2007 |
| An apparatus for transferring a replacement program into dedicated memories in a plurality of network interface cards includes: 1) a replacement program memory for storing the replacement program; 2) a first microcontroller coupled to the replacement program memory and having a first |
| 7170352 |
Apparatus and method for dynamic time-dependent amplifier biasing |
January 30, 2007 |
| A circuit for driving a capacitive load is provided. The circuit includes a differential signal sensor and a differential amplifier. The differential amplifier is arranged to drive the capacitive load. Further, the differential amplifier is arranged to receive an output voltage at on |
| 7170347 |
Offset trim circuit and method for a constant-transconductance rail-to-rail CMOS input circuit |
January 30, 2007 |
| A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output |
| 7170340 |
Apparatus and method for a class D audio power amplifier with a higher-order sigma-delta topolog |
January 30, 2007 |
| A class D power amplifier is provided to drive a low impedance load for audio applications. The amplifier includes a sigma-delta modulator circuit including three or more integrators that are arranged for third or higher order sigma-delta modulation. Also, the sigma-delta modulator c |
| 7170275 |
Method and apparatus for determining the temperature of a junction using voltage responses of th |
January 30, 2007 |
| Method and system for periodically measuring the junction temperature of a semiconductor device. The junction is excited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temper |
| 7170269 |
Low dropout regulator with control loop for avoiding hard saturation |
January 30, 2007 |
| A hard saturation mode of operation can be avoided in an LDO regulator by providing an additional feedback control loop. The additional control loop cooperates with the LDO regulator's amplifier stage and output stage to maintain at least a minimum desired voltage drop across the output |
| 7170266 |
Balanced, floating, spread-spectrum pulse width modulator circuit |
January 30, 2007 |
| A fully differential class D amplifier includes a pulse width modulator and a power stage. The pulse width modulator is arranged to employ a differential output signal provided from the power stage as a feedback signal. The pulse width modulator includes a transimpedance amplifier th |
| 7170090 |
Method and structure for testing metal-insulator-metal capacitor structures under high temperatu |
January 30, 2007 |
| A test structure and a test methodology are provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. The test structure includes a resistor formed on a region of dielectric isolation material formed in a semiconductor substrate |
| 7167569 |
Output coupling capacitor free audio power amplifier dynamically configured for speakers and hea |
January 23, 2007 |
| First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a first amplifier driving one end of a first speaker through a mechanical switch in a headphone-jack, and a second amplifier driving |
| 7167392 |
Non-volatile memory cell with improved programming technique |
January 23, 2007 |
| A non-volatile memory (NVM) cell splits its basic function, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each function. The cell structure also includes an embedded static random access memory (SRAM) cell that uti |
| 7166518 |
System and method for providing a self heating adjustable TiSi.sub.2 resistor |
January 23, 2007 |
| A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi.sub.2) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 ty |
| 7164606 |
Reverse fowler-nordheim tunneling programming for non-volatile memory cell |
January 16, 2007 |
| In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array that are to be programmed, all the electrodes of the cell are grounded. Then, an inhibitin |
| 7164317 |
Apparatus and method for a low-voltage class AB amplifier with split cascode |
January 16, 2007 |
| An op amp is arranged for low-voltage, rail-to-rail operation with a class AB output. The op amp includes a transconductance input stage, a folded cascode middle stage that includes a split cascode, a high-side driver, a low-side driver, a sampling circuit, and a split-cascode bias circu |
| 7164312 |
Apparatus and method for pop-and-click suppression with fast turn-on time |
January 16, 2007 |
| A circuit for audio amplification includes an amplifier and a first input resistor. The amplifier is arranged to provide an amplifier output signal that is based, in part, on a capacitively-coupled audio input signal. The capacitively-coupled audio input signal is based, in part, on an i |
| 7164259 |
Apparatus and method for calibrating a bandgap reference voltage |
January 16, 2007 |
| An apparatus and method for producing an output reference voltage is provided. A voltage divider is configured to provide the output reference voltage from a bandgap reference voltage. The bandgap reference voltage is applied across a biased portion of the voltage divider. Additionally, |
| 7161430 |
Low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit |
January 9, 2007 |
| A low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit for use in a ring oscillator. Operation at a reduced minimum power supply voltage is achieved via a circuit topology with selectively coordinated transistor biasing and channel dimensions. |
| 7161412 |
Analog calibration of a current source array at low supply voltages |
January 9, 2007 |
| A calibration circuit for a current source cell includes a reference current source and a transresistance amplifier forming a feedback loop for calibrating the output current of the current source cell. The reference current source supplies a reference current to a first node switcha |
| 7161393 |
Current regulation circuit |
January 9, 2007 |
| A method and circuit for providing a regulated current to a load stabilized with respect to the load current, a load voltage, and a circuit temperature. The circuit includes a power pass device, a current sense device, a voltage sense amplifier, a reference device, a temperature sens |
| 7161341 |
System, circuit, and method for auto-zeroing a bandgap amplifier |
January 9, 2007 |
| A circuit includes a bandgap core coupled to an input voltage and capable of producing an output voltage. The circuit also includes an amplifier coupled to the bandgap core. In addition, the circuit includes a switch coupling the bandgap core to an output terminal. The switch is capable |
| 7161232 |
Apparatus and method for miniature semiconductor packages |
January 9, 2007 |
| A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor ch |
| 7161216 |
Depletion-mode transistor that eliminates the need to separately set the threshold voltage of th |
January 9, 2007 |
| A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity |
