| Patent Number |
Title Of Patent |
Date Issued |
| 7230517 |
System and method for using plasma to adjust the resistance of thin film resistors |
June 12, 2007 |
| A system and method is disclosed for using plasma to adjust the resistance of a thin film resistor. In one advantageous embodiment of the invention, the resistance of a thin film resistor is increased to cause the thin film resistor to have a desired higher value of resistance. The thin |
| 7230472 |
Base current cancellation for bipolar junction transistor current summing bias voltage generator |
June 12, 2007 |
| A circuit for creating a current complementary to absolute temperature comprises a first transistor and a second transistor. A resistor for generating a current complementary to absolute temperature has a first node coupled to the emitter of the first transistor and a second node cou |
| 7230301 |
Single-crystal silicon semiconductor structure |
June 12, 2007 |
| A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the transistor, and the t |
| 7229908 |
System and method for manufacturing an out of plane integrated circuit inductor |
June 12, 2007 |
| A system and method is described for manufacturing an out of plane integrated circuit inductor. A plurality of parallel metal bars are formed on a substrate and covered with a first passivation layer. A ferromagnetic core is then deposited over the first passivation layer with its le |
| 7228113 |
SIMO/MISO transceiver for providing packet data communication with SISO transceiver |
June 5, 2007 |
| Apparatus and method for providing for packet data communication between a single-input-single-output (SISO) transceiver and a single-input-multiple-output/multiple-input-single-output (SIMO/MISO) transceiver. Receive channel coefficients representing relative strengths of individual |
| 7227476 |
Dither scheme using pulse-density modulation (dither PDM) |
June 5, 2007 |
| Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or mor |
| 7227390 |
Apparatus and method for a driver with an adaptive drive strength for a class D amplifier |
June 5, 2007 |
| A circuit for adaptively adjusting the drive strength of output power transistors in a class D amplifier is provided. The circuit includes a driver circuit and a low-voltage detect circuit. The low-voltage detect circuit is arranged to assert a low-voltage detect signal if a low supply |
| 7227245 |
Die attach pad for use in semiconductor manufacturing and method of making same |
June 5, 2007 |
| Broadly speaking, the invention pertains to substrates for use in semiconductor manufacturing. A peripheral ledge or similar structure can be provided in a die attach pad, so as to retain adhesive that may flow from the die support surface when the die is attached to the die attach p |
| 7224227 |
Apparatus and method for correction of error caused by reverse saturation current mismatch |
May 29, 2007 |
| A buffer circuit is arranged for offset cancellation between an input voltage and a buffered voltage. The buffer circuit includes two bias current sources, two p-type transistors, and two n-type transistors. Further, the base-emitter voltages of the two p-type transistors and the two |
| 7224199 |
Circuit and method for digital delay and circuits incorporating the same |
May 29, 2007 |
| A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The me |
| 7224189 |
AC/DC coupling input network with low-power common-mode correction for current-mode-logic driver |
May 29, 2007 |
| An input network is provided within an integrated circuit for interfacing with signals produced by an external CML driver apparatus. The input network includes an input for receiving the signals, and this input is coupled to a terminating impedance, a DC attenuator and an AC attenuator. |
| 7223680 |
Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin |
May 29, 2007 |
| The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q. |
| 7221918 |
Digital DC-offset correction circuit for an RF receiver |
May 22, 2007 |
| An RF receiver comprising a radio-frequency (RF) down-converter for receiving and down-converting an input RF signal to a lower frequency analog signal (e.g., an IF signal or baseband signal) and analog processing circuitry for receiving the lower frequency analog signal from the RF |
| 7221608 |
Single NMOS device memory cell and array |
May 22, 2007 |
| The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device |
| 7221134 |
Apparatus and method for flywheel current injection for a regulator |
May 22, 2007 |
| A constant on-time regulator that may use a capacitor with low ESR without needing a series resistor is provided. A capacitor is employed to AC-couple a current sense voltage into the reference signal to provide a modified reference signal. The comparator compares the feedback voltage |
| 7221036 |
BJT with ESD self protection |
May 22, 2007 |
| A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting |
| 7217966 |
Self-protecting transistor array |
May 15, 2007 |
| A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides |
| 7216307 |
Method of identifying state nodes at the transistor level in a sequential digital circuit using |
May 8, 2007 |
| The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial f |
| 7216270 |
System and method for providing testing and failure analysis of integrated circuit memory device |
May 8, 2007 |
| A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that |
| 7215147 |
System and method for providing power managed CML transmitters for use with main and auxiliary p |
May 8, 2007 |
| A system and method is provided for providing power managed common mode logic (CML) transmitters for use with main and auxiliary power sources. Power switch circuitry comprising two PMOS transistors switches the CML transmitter output circuit between a main power source node (VDD) and an |
| 7215103 |
Power conservation by reducing quiescent current in low power and standby modes |
May 8, 2007 |
| A method and circuit for automatically lowering a quiescent current at a predetermined threshold. A compact and low power current comparator is employed to detect the power consumption conditions, and issues a control signal to lower current consumption within a power management circuit. |
| 7214992 |
Multi-source, multi-gate MOS transistor with a drain region that is wider than the source region |
May 8, 2007 |
| The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than th |
| 7212588 |
Double sideband-intermediate frequency radio receiver architecture |
May 1, 2007 |
| A radio frequency (RF) receiver comprising: 1) a local oscillator (LO) circuit capable of receiving a local oscillator (LO) reference signal having frequency, LO, and a double sideband (DSB) clock signal having a frequency, DSB, and generating therefrom an in-phase product signal of |
| 7209940 |
Temperature compensated square function generator |
April 24, 2007 |
| Temperature compensation may be provided to a square function generator by adjusting a tail current of the square function generator. Temperature compensation of the square function generator may be provided, for example, by a second square function generator circuit and an error amp |
| 7209533 |
Delay locked loop with harmonic lock and hang prevention architecture |
April 24, 2007 |
| The present invention prevents the DLL from locking into the wrong phase, harmonic lock and hang. The detection is independent of temperature, voltage and process that the DLL is running. Including these mechanisms in the DLL design, the operating frequency range of the DLL can be ex |
| 7209503 |
Laser powered integrated circuit |
April 24, 2007 |
| An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive |
| 7209007 |
Combined analog signal gain controller and equalizer |
April 24, 2007 |
| An analog signal gain controller and equalizer with an increased signal bandwidth for reducing intersymbol interference (ISI) within a digital data signal. |
| 7209006 |
Differential amplifier with increased common mode loop gain at low frequencies |
April 24, 2007 |
| A differential amplifier circuit with feedback to increase common mode loop gain at low frequencies. |
| 7208981 |
Differential signal generator with built-in test circuitry |
April 24, 2007 |
| A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a |
| 7206959 |
Closed-loop, supply-adjusted ROM memory circuit |
April 17, 2007 |
| The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes fro |
| 7205923 |
Pipelined analog to digital converter that is configurable based on mode and strength of receive |
April 17, 2007 |
| A pipelined analog to digital converter (ADC) that is arranged to dynamically adapt its resolution and sampling frequency based on at least a determined mode of communication and the strength of a received wireless signal. Since standby mode data is typically communicated with a rela |
| 7205672 |
Flip chip mounted to thermal sensing element through the back side of the chip |
April 17, 2007 |
| A method for providing cooled flip chip is provided. Solder paste is placed on a back side of a flip chip. A heat sink is placed against the solder paste. The solder paste is reflowed. In addition, an apparatus is provided. Generally, a zener diode flip chip with an active side and a |
| 7205095 |
Apparatus and method for packaging image sensing semiconductor chips |
April 17, 2007 |
| An method and apparatus for fabricating a die having imaging circuitry and fabricating a lid having a transparent region and support regions having a predetermined height. The lid is fabricated by applying a photo-sensitive adhesive layer with a thickness substantially equal to the p |
| 7202744 |
Transresistance amplifier |
April 10, 2007 |
| A transresistance amplifier circuit includes an input terminal receiving an input current, an output terminal providing an output voltage indicative of the input current, a first bias current source providing a first bias current to the input terminal, a first transistor, a second tr |
| 7202538 |
Ultra low leakage MOSFET transistor |
April 10, 2007 |
| A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous |
| 7202109 |
Insulation and reinforcement of individual bonding wires in integrated circuit packages |
April 10, 2007 |
| In an integrated circuit package, a method for insulation and reinforcement of individual bonding wires in an integrated circuit package. Using an airbrush, bonding wires are sprayed and coated with an insulating material prior to the molding process. Mold flow induced short rejects |
| 7200544 |
Systems for selectively disabling timing violations in hardware description language models of i |
April 3, 2007 |
| There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit des |
| 7199440 |
Techniques for joining an opto-electronic module to a semiconductor package |
April 3, 2007 |
| The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs an |
| 7197292 |
Chopper stabilized analog multiplier |
March 27, 2007 |
| A method and circuit to eliminate an offset noise, which may be produced at or near DC (zero Hertz) in an analog, linear multiplier, is described. An input signal is chopped (converted to another frequency) by a first chopper, shifting a frequency of the input signal such that the mu |
| 7197104 |
Minimum gate delay edge counter |
March 27, 2007 |
| An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a |
| 7196589 |
Apparatus and method for dual features of frequency setting and frequency synchronization in one |
March 27, 2007 |
| An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit incl |
| 7196361 |
Cascoded bi-directional high voltage ESD protection structure |
March 27, 2007 |
| In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are |
| 7195955 |
Technique for protecting photonic devices in optoelectronic packages with clear overmolding |
March 27, 2007 |
| This disclosure describes a clear overmolding cap for protecting the photonic devices in optoelectronic packages from damage due to handling, module assembly, board assembly, and environmental exposure in field applications. The overmolding of the devices with a clear mold cap or sim |
| 7194502 |
Network interface card using physical layer microcontroller and method of operation |
March 20, 2007 |
| There is disclosed an apparatus for controlling a physical layer interface of a network interface card. The apparatus comprises: 1) a read only memory (ROM) for storing an embedded control program; 2) a random access memory for storing a downloadable software control program; and 3) a |
| 7194011 |
3GPP WCDMA receiver using pipelined apparatus and method for performing cell searches |
March 20, 2007 |
| A pipelined cell search apparatus having a primary search stage, a secondary stage and a Gold code stage. The primary stage receives a primary synchronization channel (P-SCH) signal, detects a maximum peak of a slot boundary in the P-SCH signal, and generates slot timing data from th |
| 7193553 |
Analog to digital converter with power-saving adjustable resolution |
March 20, 2007 |
| A pipelined analog to digital converter (ADC) that is arranged to dynamically adapt its resolution and sampling frequency based on at least one of a determined mode of communication, communication protocol and the strength of a received wireless signal. Since some communication proto |
| 7193456 |
Current conveyor circuit with improved power supply noise immunity |
March 20, 2007 |
| A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the powe |
| 7193450 |
Load sensing buffer circuit with controlled switching current noise (di/dt) |
March 20, 2007 |
| A load sensing buffer circuit for providing a buffered clock signal with controlled switching current noise (di/dt) in which the input clock signal is selectively gated to provide successively generated source and sink current components as part of the buffered output signal, with the |
| 7193251 |
ESD protection cluster and method of providing multi-port ESD protection |
March 20, 2007 |
| In multiple port chip circuit, an ESD protection circuit and method of protecting the ports of the multiple port circuit, includes providing a plurality of bi-directional snapback devices such as DIACs and connecting only one electrode to ground while connecting the other electrodes to t |
| 7192857 |
Method of forming a semiconductor structure with non-uniform metal widths |
March 20, 2007 |
| A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall cu |
