| Patent Number |
Title Of Patent |
Date Issued |
| 7268609 |
Logarithmic detector or logarithmic amplifier having chopper stabilized logarithmic intercept |
September 11, 2007 |
| One embodiment of the present invention is directed to an apparatus for reducing errors affecting the intercept of a logarithmic device, the apparatus including a first switching device coupled to an input of the logarithmic device. The first switching device for switches the input of |
| 7268593 |
Apparatus and method for single pin current-programmable multi-function/multi-purpose selector |
September 11, 2007 |
| A circuit for providing an output current is provided. The circuit includes a differential amplifier, a transistor having a gate that is coupled to the output of the differential amplifier, a comparator, and a sense resistor that is coupled between the drain of the transistor and the |
| 7268526 |
Switch mode power supply control circuit |
September 11, 2007 |
| An apparatus and method is arranged to dynamically adjust a pulse width (e.g., off-time pulse) associated with a switching device in a converter such as a buck converter, a boost converter, or a buck-boost regulator. A one-shot circuit is configured to dynamically initiate a pulse cycle |
| 7268410 |
Integrated switching voltage regulator using copper process technology |
September 11, 2007 |
| Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by i |
| 7268398 |
ESD protection cell with active pwell resistance control |
September 11, 2007 |
| In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage. |
| 7267930 |
Techniques for manufacturing a waveguide with a three-dimensional lens |
September 11, 2007 |
| Optical transmission structures include a waveguide and an optical lens wherein the optical lens has a sufficiently large thickness to allow the formation of a curved front lens surface that collimates transmitted light rays so that they travel within a plane that is coplanar to a wo |
| 7265705 |
Opamp and capacitor sharing scheme for low-power pipeline ADC |
September 4, 2007 |
| A first stage circuit for a high-speed, high-resolution pipeline analog-to-digital converter (ADC) implements operational amplifier (opamp) sharing and capacitor sharing to combine the sample-and-hold (SAH) and the MDAC (multiplying digital to analog converter) functions in the first |
| 7265621 |
Fully differential operational amplifier with fast settling time |
September 4, 2007 |
| An operational amplifier includes a pair of differential input transistors, a pair of cascode transistors and a keep-alive circuit. The pair of differential input transistors is connected together at the source terminals and the gate terminals of the input transistors receive a pair |
| 7265606 |
Apparatus and method for a boot strap circuit for a boost voltage converter |
September 4, 2007 |
| A boost converter with a flying capacitor topology is provided. The flying capacitor is charged during a first half of a cycle. During a second half of the cycle, the output voltage of the boost converter is supplied from Vdd until the output voltage approximately reaches Vdd. At that po |
| 7265599 |
Flipflop that can tolerate arbitrarily slow clock edges |
September 4, 2007 |
| A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected together, and to electric |
| 7265530 |
Adaptive slope compensation for switching regulators |
September 4, 2007 |
| A system, method, and apparatus are arranged to provide adaptive slope compensation in a switching regulator that includes an inductor. A control loop of the switching regulator is responsive to a ramp signal. A ramp generator that includes a capacitor circuit and a current source pr |
| 7262701 |
Antenna structures for RFID devices |
August 28, 2007 |
| An improved antenna structure for RFID tags uses a pair of bent dipole antennas having arms that extend substantially about an outer edge of an RFID substrate. The antennas can be adjusted to resonance at about a half-wavelength of an applied electromagnetic field in the conductive m |
| 7262111 |
Method for providing a deep connection to a substrate or buried layer in a semiconductor device |
August 28, 2007 |
| A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial s |
| 7260808 |
Method and metric for low power standard cell logic synthesis |
August 21, 2007 |
| Pseudo area values, which represent standard cell power dissipation, are substituted for physical standard cell areas in a standard cell library. As a result, when a logic synthesizer synthesizes a gate level netlist from hardware description language (HDL) code, the synthesized netlist |
| 7259632 |
Method for cascoding amplifiers by modulating isolated power supply reference points |
August 21, 2007 |
| A method for cascading a first amplifier stage and a second amplifier stage includes coupling the output terminal of the first amplifier stage to the power supply reference point of the second amplifier stage, modulating the power supply reference point of the second amplifier stage |
| 7259610 |
Static CMOS logic level shift circuit with a low logic input count high switching speed and low |
August 21, 2007 |
| A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting r |
| 7259460 |
Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated |
August 21, 2007 |
| Aspects of the invention recite wire bonding on thinned portions of a lead-frame that is configured for use in an IC package. A harder lead-frame material, improved adhesive tape, and various structural features of the lead-frame itself, in various combinations or subcombinations, fa |
| 7259411 |
Vertical MOS transistor |
August 21, 2007 |
| A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transis |
| 7256651 |
System and method for providing a constant swing high-gain complementary differential limiting a |
August 14, 2007 |
| A system and a method are disclosed for providing a constant swing high-gain complementary differential limiting amplifier. High gain for the differential amplifier is created by providing a current to the driving transistors that is a combination of any of (a) constant current, (b) |
| 7254791 |
Method of measuring test coverage of backend verification runsets and automatically identifying |
August 7, 2007 |
| The quality assurance of all released runset files should ideally be 100% complete to ensure the best quality of the runsets. This means that the designs used for testing should be sufficient to test all of the design rules with the appropriate data in the runset to reach 100% coverage, |
| 7254198 |
Receiver system having analog pre-filter and digital equalizer |
August 7, 2007 |
| A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (y.sub.k), or a first intermediate analog signal generat |
| 7253700 |
Circuit for controlling a linear-in-decibels attenuator circuit using an analog control signal |
August 7, 2007 |
| A circuit for a digitally operating linear-in-decibels attenuator circuit controlled using an analog control signal. The attenuator circuit includes a resistor ladder, digitally controlled switches, and a flash analog-to-digital converter. The resistive ladder includes resistances co |
| 7253598 |
Bandgap reference designs with stacked diodes, integrated current source and integrated sub-band |
August 7, 2007 |
| The performance of a bandgap reference circuit is improved by increasing the .DELTA.VBE, and thereby correspondingly decreasing the input sensitivity of the error amplifier in the control loop. The .DELTA.VBE can be increased by presenting stacked diode configurations at the amplifie |
| 7253589 |
Dual-source CMOS battery charger |
August 7, 2007 |
| A circuit for charging a battery by selecting among two available power sources while providing overcharging and temperature protection to the battery and managing a charging current is described. A power pass and sense circuit is arranged to provide charge voltage from either power |
| 7253078 |
Method and apparatus for forming an underfill adhesive layer |
August 7, 2007 |
| An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive has partially cured, |
| 7252432 |
Efficient method of sharing diode pins on multi-channel remote diode temperature sensors |
August 7, 2007 |
| A multi-channel remote diode temperature sensor includes a variable current supply configured to provide a base or an elevated current, a bias circuit, an analog-to-digital converter having a first and second input terminals, a logic block and a switch arrangement. The switch arrange |
| 7250884 |
Analog-to-digital converters for control loop applications |
July 31, 2007 |
| An analog-to-digital converter error detector suitable for single-chip control loop applications employs a single comparator determining the difference between an initial input voltage and a reference voltage in one or more conversion iterations, with the difference reduced in nonlin |
| 7250842 |
MEMS inductor with very low resistance |
July 31, 2007 |
| A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utiliz |
| 7250841 |
Saucer-shaped half-loop MEMS inductor with very low resistance |
July 31, 2007 |
| A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a |
| 7250813 |
Split amplifier architecture for cross talk cancellation |
July 31, 2007 |
| An amplifier circuit includes a first amplifier and a second amplifier and sets of switching devices controlled by a bistate control signal. The bistate control signal is in the first state to cause the first and second sets of switching devices to configure the first amplifier and the |
| 7250807 |
Threshold scaling circuit that minimizes leakage current |
July 31, 2007 |
| The leakage current output by a MOS transistor is minimized by varying a back bias voltage across a range of voltages, and detecting the back bias voltage within the range that minimizes the leakage current output by the MOS transistor. The detected back bias voltage is then applied to t |
| 7250348 |
Apparatus and method for packaging semiconductor devices using a patterned photo sensitive film |
July 31, 2007 |
| A method and apparatus for packaging semiconductor devices using patterned laminate films to reduce stress buffering. The method includes fabricating a semiconductor die having thin film resistors and bond pads formed on an active surface. A film layer is formed onto the active surfa |
| 7250318 |
System and method for providing automated sample preparation for plan view transmission electron |
July 31, 2007 |
| A system and method is described for providing automated sample preparation for plan view transmission electron microscopy. A sample wafer is microcleaved from a semiconductor wafer and mounted on a first support stub. Then the sample wafer is cut with an automated diamond sawing too |
| 7250310 |
Process for forming and analyzing stacked die |
July 31, 2007 |
| In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical forc |
| 7248098 |
Curvature corrected bandgap circuit |
July 24, 2007 |
| An apparatus and method provide for curvature corrected temperature variations in a band-gap reference circuit. The apparatus includes a band-gap cell, an IPTAT circuit, a resistor, and a feedback circuit. The band-gap cell is arranged to provide a band-gap voltage. The resistor circ |
| 7248080 |
Power supply switching at circuit block level to reduce integrated circuit input leakage current |
July 24, 2007 |
| Leakage currents at IC inputs can be avoided while the IC is disabled by providing a switch that is responsive to deactivation of an enable input to isolate functional circuitry of the IC from one of the power supply nodes of the IC. This eliminates power supply current while the IC is |
| 7247942 |
Techniques for joining an opto-electronic module to a semiconductor package |
July 24, 2007 |
| The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs an |
| 7247544 |
High Q inductor integration |
July 24, 2007 |
| In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric. |
| 7247209 |
Dual outlet nozzle for the combined edge bead removal and backside wash of spin coated wafers |
July 24, 2007 |
| An apparatus and method for the improved combined edge bead removal and backside wash of spin coated semiconductor wafers is disclosed. This is preferably accomplished by providing a nozzle having a plurality of outlets adapted for the ejection of a cleaning fluid onto the backside of |
| 7246334 |
Topological analysis based method for identifying state nodes in a sequential digital circuit at |
July 17, 2007 |
| State nodes in a sequential digital circuit are identified using a graph-based method based upon the topology of the circuit. In accordance with the method, the device level circuit netlist is reduced to a graph representation using a well-defined set of rules. The unique properties |
| 7242223 |
Clock frequency monitor |
July 10, 2007 |
| A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a cl |
| 7241643 |
Wafer level chip scale package |
July 10, 2007 |
| A wafer level fabricated integrated circuit package having an air gap formed between the integrated circuit die of the package and a flexible circuit film located over and conductively attached to the die though raised interconnects formed on the die is described. The flexible circuit |
| 7240222 |
Using ACPI power button signal for remotely controlling the power of a PC |
July 3, 2007 |
| In a computer system that includes processing, memory and I/O modules and ACPI for outputting an ONCTL signal to a power supply unit. The power supply is configured to output a power off signal indicative of power off state and power on signal indicative of power on state. There is provi |
| 7239712 |
Inductor-based MEMS microphone |
July 3, 2007 |
| An inductor-based integrated MEMS microphone and a method of making the microphone is provided. The microphone structure includes a vibrating inductor that is suspended over another stationary inductor such that the magnetic field induced from one inductor induces an electrical potential |
| 7239558 |
Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a sing |
July 3, 2007 |
| A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that |
| 7238620 |
System and method for providing a uniform oxide layer over a laser trimmed fuse with a different |
July 3, 2007 |
| A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a f |
| 7238577 |
Method of manufacturing self-aligned n and p type stripes for a superjunction device |
July 3, 2007 |
| A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alternating stripes e |
| 7238553 |
Method of forming a high-voltage silicon controlled rectifier structure with improved punch thro |
July 3, 2007 |
| When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantia |
| 7236203 |
Video circuitry for controlling signal gain and reference black level |
June 26, 2007 |
| An apparatus and method for controlling signal gain and reference black level of a video signal. Magnitudes of signal gain and reference voltage for a subject video signal are determined by a common digital control signal, while the reference voltage determines the reference black level. |
| 7236117 |
Apparatus and method for ping-pong mismatch correction |
June 26, 2007 |
| An analog front-end (AFE) circuit may include a correlated double sampler (CDS) with a ping-pong architecture, and a ping-pong mismatch correction circuit. The CDS employs a ping data path during ping phases, and employs a pong data path during pong phases. The ping-pong mismatch correct |
