| Patent Number |
Title Of Patent |
Date Issued |
| T956003 |
Interconnect logic for a serial processor |
March 1, 1977 |
| the interconnect logic between a main control unit and the data handling register of a serial processor is formed of a programmable logic array (PLA). The serial processor includes a main control unit, a plurality of registers and PLA interconnect logic. The interconnect logic decodes an |
| RE40942 |
Integrated digital signal processor/general purpose CPU with shared internal memory |
October 20, 2009 |
| An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose |
| RE39854 |
Lead frame chip scale package |
September 25, 2007 |
| A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape se |
| RE39812 |
Method and apparatus which allows devices with multiple protocol capabilities to configure to a |
September 4, 2007 |
| An apparatus matches the configuration of a first station of a local area network to the configuration of the second station of the local area network. The first station detects a protocol advertisement from the second station that indicates a protocol in which the second station is |
| RE38789 |
Semiconductor wafer having a bottom surface protective coating |
September 6, 2005 |
| Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the |
| RE31967 |
Gang bonding interconnect tape for semiconductive devices and method of making same |
August 13, 1985 |
| A gang bonding interconnect tape for use in an automatic bonding machine for gang bonding of semiconductive devices is fabricated by depositing a series of electrically insulative support structures, such as rings of epoxy resin, onto a metallic tape, as of copper, there being at least o |
| D602432 |
Reverse current blocking module for use in a solar power installation |
October 20, 2009 |
|
| D432124 |
Portable internet terminal |
October 17, 2000 |
|
| D366466 |
Card reader |
January 23, 1996 |
|
| 7612609 |
Self-stabilizing differential load circuit with well controlled complex impedance |
November 3, 2009 |
| A circuit for providing a self-stabilizing, differential load circuit with well controlled complex impedance to an amplifier is described. According to an embodiment, two pairs of transistors in a cross-coupled configuration, a degeneration resistor for each transistor, and parasitic |
| 7612435 |
Method of packaging integrated circuits |
November 3, 2009 |
| A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that in |
| 7608482 |
Integrated circuit package with molded insulation |
October 27, 2009 |
| A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving ot |
| 7606955 |
Single wire bus for connecting devices and methods of operating the same |
October 20, 2009 |
| A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device i |
| 7605659 |
Gain adjustment for programmable gain amplifiers |
October 20, 2009 |
| A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the |
| 7605635 |
Threshold control circuitry for multiple current signal receivers |
October 20, 2009 |
| Calibration circuitry and method for maintaining constant signal detection thresholds for multiple signal receivers that receive data signals in the form of current signals. A value of one of the incoming current signals having a predetermined signal pattern is detected and used to gener |
| 7605619 |
I/O protection under over-voltage and back-drive conditions by single well charging |
October 20, 2009 |
| In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protect |
| 7602666 |
Method of forming a unique number |
October 13, 2009 |
| A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit |
| 7602641 |
Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for t |
October 13, 2009 |
| A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM |
| 7602328 |
Data conversion diagnostic bit in a data converter |
October 13, 2009 |
| A data converter (10) for digitizing an analog input signal and providing digital output data at one or more conversion cycles includes a logic circuit (28) for generating a data conversion diagnostic bit (38) having first and second logical states. The data conversion diagnostic bit |
| 7602267 |
MEMS actuator and relay with horizontal actuation |
October 13, 2009 |
| A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the |
| 7602166 |
System and method for providing a digital self-adjusting power supply that provides a substantia |
October 13, 2009 |
| A system and method is disclosed that provides a digital self-adjusting power supply for semiconductor digital circuits. The power supply provides a substantially constant minimum supply voltage with regard to process corner, junction temperature, external voltage source, load variat |
| 7602158 |
Power circuit for generating non-isolated low voltage power in a standby condition |
October 13, 2009 |
| A power circuit generating a non-isolating low voltage power supply using a capacitive AC voltage drop in standby. Specifically, the power circuit includes an AC connector that generates a first AC input and a second AC input that are opposite in phase. The power circuit also includes fi |
| 7598829 |
MEMS actuator and relay with vertical actuation |
October 6, 2009 |
| A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the |
| 7598715 |
Apparatus and method for reverse current correction for a switching regulator |
October 6, 2009 |
| A synchronous switching voltage regulator circuit is provided. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification, or vice versa. During the gradual transition, the error voltage is |
| 7598575 |
Semiconductor die with reduced RF attenuation |
October 6, 2009 |
| The attenuation of an RF signal on a metal trace in a semiconductor die is substantially reduced by utilizing a number of RF blocking structures that lie on the surface of the substrate directly below the metal trace that carries the RF signal. The RF blocking structures include an i |
| 7598122 |
Die attach method and microarray leadframe structure |
October 6, 2009 |
| In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a |
| 7595685 |
Power efficient and fast settling bias current generation circuit and system |
September 29, 2009 |
| Bias current generation systems are disclosed. In one embodiment, a bias current generation system comprises a proportional to absolute temperature (PTAT) current source generating a PTAT current, a constant current source generating a constant current, a first current mirror forward |
| 7595627 |
Voltage reference circuit with complementary PTAT voltage generators and method |
September 29, 2009 |
| A voltage reference circuit is provided. The voltage reference circuit includes a first PTAT voltage generator and an amplifier. The first PTAT voltage generator is operable to generate a first PTAT voltage. The amplifier, which is coupled to the first PTAT voltage generator, compris |
| 7595622 |
System and method for providing a sample and hold circuit for maintaining an output voltage of a |
September 29, 2009 |
| A system and method are disclosed for maintaining an output voltage of a constant current source circuit. A constant current source circuit is provided that comprises a voltage regulator, a first feedback loop and a second feedback loop that are connected to the voltage regulator, and a |
| 7595244 |
Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical bo |
September 29, 2009 |
| Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor body. Gate electrodes (74 or 94) are defined s |
| 7595243 |
Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor |
September 29, 2009 |
| A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor ("IGFET") (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally fabricated to be of mater |
| 7590880 |
Circuitry and method for detecting and protecting against over-clocking attacks |
September 15, 2009 |
| The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for providing a delayed signal of the test signal, and circuitry for comparing the logical sta |
| 7589517 |
Adaptive slope compensation for switching regulators |
September 15, 2009 |
| A system, method, and apparatus are arranged to provide adaptive slope compensation in a switching regulator that includes an inductor. A control loop of the switching regulator is responsive to a ramp signal. A ramp generator that includes a capacitor circuit and a current source pr |
| 7589397 |
System and method for providing a uniform oxide layer over a laser trimmed fuse with a different |
September 15, 2009 |
| A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a f |
| 7586792 |
System and method for providing drain avalanche hot carrier programming for non-volatile memory |
September 8, 2009 |
| A system and method are disclosed for providing drain avalanche hot carrier (DAHC) programming for non-volatile memory (NVM) applications. A memory cell of the present invention comprises a program transistor and a control capacitor, each having a gate coupled together to form a floating |
| 7586064 |
Method and system for providing thermostatic temperature control in an integrated circuit |
September 8, 2009 |
| A method for providing thermostatic temperature control in an integrated circuit is provided that includes internally heating the integrated circuit until the integrated circuit reaches an elevated temperature and holding the integrated circuit at the elevated temperature. For a part |
| 7585784 |
System and method for reducing etch sequencing induced downstream dielectric defects in high vol |
September 8, 2009 |
| A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three factors have been identified as causes of the defects. The three factors are: (1) phospho |
| 7585775 |
System and method for faceting a masking layer in a plasma etch to slope a feature edge |
September 8, 2009 |
| A method is disclosed for applying a plasma etch process to facet a masking layer in a semiconductor device by creating sloped surfaces in the masking layer. The masking layer is plasma etched with a plasma that has a high sputter etch component. The plasma etch process removes mater |
| 7584533 |
Method of fabricating an inductor structure on an integrated circuit structure |
September 8, 2009 |
| A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy mag |
| 7584314 |
Universal serial-to-parallel and parallel-to-serial cable interface and method |
September 1, 2009 |
| A universal cable interface and associated system and method are provided for coupling a transmission medium to a processing device. The universal cable interface can selectively operate in a first (input) mode and a second (output) mode. The universal cable interface can also handle |
| 7583138 |
System and method for controlling an error amplifier between control mode changes |
September 1, 2009 |
| A system and a method are disclosed for controlling an error amplifier between control mode changes. An error amplifier comprises a first stage that comprises a first current source and a second stage that comprises a second current source and at least one compensation component that is |
| 7582954 |
Optical leadless leadframe package |
September 1, 2009 |
| Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first s |
| 7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level |
August 25, 2009 |
| An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same |
| 7581131 |
Method and system for balancing clock trees in a multi-voltage synchronous digital environment |
August 25, 2009 |
| A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first mirrored clock signal in a second voltage domain. Similarly, a second source clock signal is |
| 7581120 |
System and method for providing multi-point calibration of an adaptive voltage scaling system |
August 25, 2009 |
| A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the a |
| 7580428 |
3GPP WCDMA receiver using pipelined apparatus and method for performing cell searches |
August 25, 2009 |
| A pipelined cell search apparatus having a primary search stage, a secondary stage and a Gold code stage. The primary stage receives a primary synchronization channel (P-SCH) signal, detects a maximum peak of a slot boundary in the P-SCH signal, and generates slot timing data from th |
| 7579906 |
System and method for providing a low power low voltage data detection circuit for RF AM signals |
August 25, 2009 |
| A system and method is disclosed for demodulating RF amplitude modulated signals in a demodulator circuit of an EPC0 compliant RFID tag. One advantageous embodiment of the invention comprises first and second input ports, a +ve envelope detector circuit for each of the first and second |
| 7579819 |
Apparatus and method for flywheel current injection for a regulator |
August 25, 2009 |
| A constant on-time regulator that may use a capacitor with low ESR without needing a series resistor is provided. A capacitor is employed to AC-couple a current sense voltage into the reference signal to provide a modified reference signal. The comparator compares the feedback voltage |
| 7579683 |
Memory interface optimized for stacked configurations |
August 25, 2009 |
| A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of |
| 7579642 |
Gate-enhanced junction varactor |
August 25, 2009 |
| A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. |
