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National Semiconductor Corporation Patents
National Semiconductor Corporation
Santa Clara, CA
No. of patents:

Patent Number Title Of Patent Date Issued
T956003 Interconnect logic for a serial processor March 1, 1977
the interconnect logic between a main control unit and the data handling register of a serial processor is formed of a programmable logic array (PLA). The serial processor includes a main control unit, a plurality of registers and PLA interconnect logic. The interconnect logic decodes an
RE40942 Integrated digital signal processor/general purpose CPU with shared internal memory October 20, 2009
An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose
RE39854 Lead frame chip scale package September 25, 2007
A method for producing chip scale IC packages includes the step of mounting a lead frame panel on a temporary support fixture in order to provide support and protection during the manufacturing process. An embodiment of the temporary support fixture includes a sheet of sticky tape se
RE39812 Method and apparatus which allows devices with multiple protocol capabilities to configure to a September 4, 2007
An apparatus matches the configuration of a first station of a local area network to the configuration of the second station of the local area network. The first station detects a protocol advertisement from the second station that indicates a protocol in which the second station is
RE38789 Semiconductor wafer having a bottom surface protective coating September 6, 2005
Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the
RE31967 Gang bonding interconnect tape for semiconductive devices and method of making same August 13, 1985
A gang bonding interconnect tape for use in an automatic bonding machine for gang bonding of semiconductive devices is fabricated by depositing a series of electrically insulative support structures, such as rings of epoxy resin, onto a metallic tape, as of copper, there being at least o
D602432 Reverse current blocking module for use in a solar power installation October 20, 2009
D432124 Portable internet terminal October 17, 2000
D366466 Card reader January 23, 1996
8588289 Adaptive signal equalizer with segmented coarse and fine controls November 19, 2013
Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.
8587275 Instantaneous average current measurement method November 19, 2013
Circuitry and method for providing a signal indicative of instances of conduction of average inductor current in a DC-to-DC voltage converter. Such signal identifies a time when the instantaneous average current being conducted by the inductor in a DC-to-DC voltage converter can be m
8587268 System and method for providing an active current assist with analog bypass for a switcher circu November 19, 2013
A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current
8581579 Magneto electric sensor with injected up-conversion or down-conversion November 12, 2013
A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electric
8572426 Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) s October 29, 2013
An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The
8564092 Power convertor device and construction methods October 22, 2013
In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat d
8564062 High voltage MOS array with gate contact on extended drain region October 22, 2013
In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space.
8299578 High voltage bipolar transistor with bias shield October 30, 2012
In a SOI process, a high voltage BJT structure with BV.sub.CEO versus F.sub.T control is provided by including a bias shield over the laterally extending collector region and controlling the bias of the shield.
8299531 CMOS ESD clamp with input and separate output voltage terminal for ESD protection October 30, 2012
In a snapback NMOS ESD protection structure, the output voltage presented to an internal circuit for ESD protection is limited by providing for a separate output terminal at a lower voltage than the input terminal. The voltage drop between the two terminals is achieved by connecting the
8298901 Method for manufacturing bipolar transistors October 30, 2012
An improved method for manufacturing bipolar transistors is disclosed. The method for forming a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base,
8298871 Method and leadframe for packaging integrated circuits October 30, 2012
A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opp
8287751 System and method for providing a continuous bath wetdeck process October 16, 2012
A system and method is described for providing a continuous bath wetdeck process for use in the manufacture of semiconductor wafers. The invention provides a method for extending an effective working life of a chemical bath of the type that comprises a chemical bath liquid within a chemi
8284600 5-transistor non-volatile memory cell October 9, 2012
A non-volatile memory (NVM) cell comprises an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node; a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a
8283760 Lead frame interconnect scheme with high power density October 9, 2012
An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded
8282846 Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad f October 9, 2012
A metal interconnect structure, which includes a bond pad, an overlying anti-reflective coating layer, an overlying passivation layer, and an opening that exposes a top surface of the bond pad, eliminates corrosion resulting from the anti-reflective layer being exposed to moisture during
8279644 Method and system for providing maximum power point tracking in an energy generating system October 2, 2012
A method for providing a maximum power point tracking (MPPT) process for an energy generating device is provided. The method includes coupling a local converter to the energy generating device. A determination is made regarding whether the local converter is operating at or below a maxim
8278995 Bandgap in CMOS DGO process October 2, 2012
Bandgap voltage reference circuitry capable of operating at very low power supply voltages. The current source for driving the core bandgap voltage reference is implemented with insulated gate field effect transistors having low threshold voltages. Voltage clamp circuitry protects th
8278886 Power FET gate charge recovery October 2, 2012
A circuit for recovering charge at the gate of an output transistor arranged to drive the output of a switching circuit such as a switching regulator or controller. A substantial portion of the charge for each switching cycle is recovered under a wide range of load conditions for the
8275341 Fixed point FIR filter with adaptive truncation and clipping and wireless mobile station using s September 25, 2012
A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier rece
8275340 Fixed point FIR filter with adaptive truncation and clipping and wireless mobile station using s September 25, 2012
A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier rece
8275339 Fixed point FIR filter with adaptive truncation and clipping and wireless mobile station using s September 25, 2012
A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier rece
8274824 High-performance CMOS-compatible non-volatile memory cell and related method September 25, 2012
A memory cell includes a control gate and a transistor having a gate, a source junction, and a drain junction. The gate is coupled to the control gate, and the source junction and the drain junction are asymmetrical. For example, a channel doping associated with the source junction may b
8274129 Power transistor with improved high-side operating characteristics and reduced resistance and re September 25, 2012
A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes form
8273608 Method of forming a copper-compatible fuse target September 25, 2012
A copper-compatible fuse target is fabricated by forming a target structure at the same time that a trace structure is formed on a passivation layer, followed by the formation of an overlying non-conductive structure. After the overlying non-conductive structure has been formed, a pa
8270463 System and method for adaptively equalizing data signals with higher and lower data rates September 18, 2012
System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalize
8269558 Power supply controller for a multi-gain step RF power amplifier September 18, 2012
A power supply controller controls the power supply voltage provided to a multi-gain step RF power amplifier to increase the efficiency of the RF power amplifier when the different gains of the RF power amplifier are selected and, thereby, reduce the power consumed by the multi-gain step
8267303 Wire bonding apparatus with a textured capillary surface enabling high-speed wedge bonding of wi September 18, 2012
Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems.
8258026 Fabrication of semiconductor architecture having field-effect transistors especially suitable fo September 4, 2012
An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of
8253208 Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with August 28, 2012
A gate dielectric layer (500, 566, or 700) of an insulated-gate field-effect transistor (110, 114, or 122) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (502, 568, or 702) from significantly penetrating t
8248885 Sub-beam forming receiver circuitry for ultrasound system August 21, 2012
Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.
8247862 Method of enhancing charge storage in an E.sup.2PROM cell August 21, 2012
A method is provided for enhancing charge storage in an E.sup.2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage
8241975 System and method for providing low voltage high density multi-bit storage flash memory August 14, 2012
A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate
8238414 Sliding error sampler (SES) for latency reduction in the PWM path August 7, 2012
A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation
8237467 Resistor-programmable device at low voltage August 7, 2012
A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such
8237177 Fully silicon ALED-photodiode optical data link module August 7, 2012
In a silicon-based light emitting diode-photodiode (LED-PD) arrangement, the LED is implemented as an avalanche LED (ALED) and the ALED and PD are integrated into a common integrated circuit. The ALED is formed around a cross-shaped PD and is separated from the PD by a deep trench region
8222716 Multiple leadframe package July 17, 2012
Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and
8222065 Method and system for forming a capacitive micromachined ultrasonic transducer July 17, 2012
A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide f
8220933 Method and apparatus for data transfer using an optical link in a projector system July 17, 2012
A projection system for projecting an output image. The projection system comprises 1) a plurality of laser diodes, each laser diode generating a light beam; 2) combiner optics for combining light beams from the laser diodes to generate an output light beam; and a MEMS mirror module for
8213227 4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure July 3, 2012
A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-c
8212799 Apparatus and method for performing response time compensation of a display between gray level t July 3, 2012
An apparatus and method for performing response time compensation. The apparatus described includes a first response time compensation (RTC) module for providing boosted gray level values when transitioning only from a previous gray level of zero to a first current gray level for a c
8212320 High voltage tolerant ESD device July 3, 2012
In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.

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