| Patent Number |
Title Of Patent |
Date Issued |
| 7602256 |
Systems and techniques for auto-calibration and fast tuning of voltage controlled oscillators in |
October 13, 2009 |
| Systems, circuits, and techniques for the calibration and fast tuning of VCOs in PLLs are provided. Information for coarse tuning before normal operation are calculated and stored. These systems and techniques decrease significantly the time needed for a PLL to transition from one fr |
| 7532079 |
Digital tuning of crystal oscillators |
May 12, 2009 |
| Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating |
| 7521976 |
Low power high speed latch for a prescaler divider |
April 21, 2009 |
| A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of |
| 7474885 |
Passive subharmonic mixer |
January 6, 2009 |
| Embodiments feature a circuit that includes a first set of differential switches to generate a first mixer output. The first set includes source terminals, a differential input terminal, gate terminals, and first mixer output terminals. For the first set, the source terminals are coupled |
| 7299020 |
Tunable multi-band receiver by on-chip selectable filtering |
November 20, 2007 |
| A multiple frequency RF communications receiver is disclosed which permits greater integration on standard silicon chips and consumes less power than previous receivers. A new method for selecting the various frequency bands with a high amount of isolation and low power consumption is |
| 7248850 |
Passive subharmonic mixer design |
July 24, 2007 |
| A mixer design is described that permits greater integration on standard silicon chips with an improvement in power and linearity compared to previous mixer designs, enabling low-power, high performance RF reception. |
| 7069482 |
ROM error-correction control |
June 27, 2006 |
| To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals represent addresses of |
| 6981187 |
Test mode for a self-refreshed SRAM with DRAM memory cells |
December 27, 2005 |
| A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a |
| 6920528 |
Smart memory |
July 19, 2005 |
| A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is a multi-media RAM (MMRAM) chip |
| 6757207 |
Refresh miss detect circuit for self-refreshing DRAM |
June 29, 2004 |
| A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh request control sig |
| 6741515 |
DRAM with total self refresh and control circuit |
May 25, 2004 |
| Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator a |
| 6735142 |
Power-up control circuit with a power-saving mode of operation |
May 11, 2004 |
| A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply |
| 6721210 |
Voltage boosting circuit for a low power semiconductor memory |
April 13, 2004 |
| An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a |
| 6713855 |
Dual die memory |
March 30, 2004 |
| A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout |
| 6694448 |
SRAM row redundancy |
February 17, 2004 |
| A fuse-controlled, row-redundancy control system and method for a SRAM includes a multi-bit, defective-row storage array of static circuits that are programmed to store one of the address bits of a predetermined defective row of the SRAM and that includes a single fuse. The single fuse |
| 6681287 |
Smart memory |
January 20, 2004 |
| A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is a multi-media RAM (MMRAM) chip |
| 6643216 |
Asynchronous queuing circuit for DRAM external RAS accesses |
November 4, 2003 |
| A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial ac |
| 6593646 |
Dual die memory |
July 15, 2003 |
| A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout |
| 6559678 |
Node predisposition circuit |
May 6, 2003 |
| A node predisposition circuit for driving an output node of an output buffer circuit is provided which is formed of a delay circuit, a pre-charge pull-up circuit, and a pre-charge pull-down circuit. The pre-charge pull-up and pull-down circuits are used for pre-charging the output no |
| 6493414 |
Die information logic and protocol |
December 10, 2002 |
| An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM), the fuses are electrically |
| 6355980 |
Dual die memory |
March 12, 2002 |
| A double-sized chip assembly and method is provided for two back-to-back integrated-circuit chips which both have the same fabrication mask sets. An electrically-selectable bonding-pad connection option alternatively provides a standard, non-reversed, option NRO for a bonding-pad layout |
| 6240029 |
Memory column redundancy |
May 29, 2001 |
| An incoming memory address signal is compared and matched with static signals provided by a fuse array that represents an address of a defective memory column that is being replaced by a redundant memory column in a memory chip. Each section of a memory is provided with a redundant memor |
| 6167543 |
Memory test mode circuit |
December 26, 2000 |
| A memory-test-mode detection circuit for an integrated circuit uses one or more of the input pins of an integrated circuit to detect at least one non-standard signal level. To avoid false triggering several other non-standard logic levels can also be used with some of the other input |
| 5963071 |
Frequency doubler with adjustable duty cycle |
October 5, 1999 |
| An adjustable duty-cycle circuit includes an EXCLUSIVE-OR circuit for combining a divided reference input signal at a frequency .function..sub.IN /2 with a variably delayed divided reference input signal to provide an output frequency V.sub.O at .function..sub.IN with an adjustable d |
| 5942932 |
Circuit and method for preventing latch-up in a CMOS semiconductor device |
August 24, 1999 |
| A circuit and method for preventing latch-up in a CMOS semiconductor device. In an n-type substrate and p-type well region semiconductor, the method comprises the steps of pulling V.sub.sub of the substrate terminal to V.sub.CC and pulling V.sub.well of the well region terminal to V.sub. |
