| Patent Number |
Title Of Patent |
Date Issued |
| 7256462 |
Semiconductor device |
August 14, 2007 |
| The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor |
| 7256456 |
SOI substrate and semiconductor integrated circuit device |
August 14, 2007 |
| A semiconductor IC device includes a base substrate comprising P.sup.--type silicon, a first P.sup.+-type silicon layer is provided on the base substrate, and an N.sup.+-type silicon layer and a second P.sup.+-type silicon layer are provided in the same layer thereon. The impurity co |
| 7254688 |
Data processing apparatus that shares a single semiconductor memory circuit among multiple data |
August 7, 2007 |
| Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or 202-2) ending control of a semiconductor memory circuit (201) supplies a clock enable signal |
| 7254081 |
Semiconductor memory device |
August 7, 2007 |
| A semiconductor memory device has: a word driver configured to apply a driving voltage to a word line connected to a memory cell; and an internal power supply circuit configured to supply the driving voltage to the word driver and to apply a substrate voltage to back gates of transis |
| 7253754 |
Data form converter between serial and parallel |
August 7, 2007 |
| A data form converter allowing parallel-to-serial or serial-to-parallel conversion at various conversion ratios is disclosed. A frequency divider divides an input clock in frequency at a variable frequency division ratio to produce a single frequency-divided clock. A data shift circuit |
| 7253515 |
Semiconductor package featuring metal lid member |
August 7, 2007 |
| In a semiconductor package, a semiconductor chip is mounted on a wiring board or package board. A lid member defines a recess for accommodating the semiconductor chip, and is mounted on the package board so that the semiconductor chip is accommodated in the recess of the lid member. A |
| 7253478 |
Semiconductor device |
August 7, 2007 |
| The semiconductor device comprises: a semiconductor substrate (N.sup.+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P.sup.+ implanted layer 114) at relatively high concentration, formed on the sem |
| 7253363 |
Circuit board |
August 7, 2007 |
| A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric lay |
| 7250891 |
Gray scale voltage generating circuit |
July 31, 2007 |
| A gray scale voltage generating circuit includes a first resistor ladder circuit, connected between a high voltage power supply terminal and a low voltage power supply terminal and having nodes for outputting respective reference voltages, a second resistor ladder circuit, connected betw |
| 7250758 |
Inspection method and apparatus using scanning laser SQUID microscope |
July 31, 2007 |
| A non-destructive method of narrowing down the location of a failure in a sample includes a first step of acquiring first and second images of magnetic-field distributions obtained by scanning a laser beam irradiating first and second samples, respectively, and if there is a differen |
| 7250740 |
Method and apparatus for generating pulse-width modulated waveform |
July 31, 2007 |
| In a method of generating pulse-width modulated waveform, the cycle of a carrier wave for the waveform is determined together with a first dead time value and a second dead time value both of which are set in a plurality of up-down counters, respectively. Using the plurality of the u |
| 7250661 |
Semiconductor memory device with plural source/drain regions |
July 31, 2007 |
| A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of |
| 7250652 |
Nonvolatile semiconductor memory device including an assistant gate formed in a trench |
July 31, 2007 |
| A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The se |
| 7249336 |
Automatic wiring method for semiconductor integrated circuit, program for the same, and semicond |
July 24, 2007 |
| A controller arranges macrocells having power terminals and ground terminals in desired positions on a semiconductor chip. The power terminals and ground terminals are arranged in a fourth line layer such that the centers of square power terminals and ground terminals substantially c |
| 7248533 |
Semiconductor circuit apparatus with power save mode |
July 24, 2007 |
| A semiconductor circuit apparatus comprises a substrate and a circuit block including a memory formed on the substrate. The circuit block performs regular operations at a first power supply voltage in an active mode, and a part of the circuit block is stopped and the memory keeps sto |
| 7248254 |
Gamma correcting circuit and panel drive apparatus equipped with gamma correcting circuit |
July 24, 2007 |
| Each gamma characteristic adjusting unit in a gamma correcting circuit selects a reference voltage from basic voltages generated by a basic voltage generating circuit based on correction adjustment data and selects a reference-voltage output terminal from reference-voltage output ter |
| 7248115 |
Differential amplifier operable in wide range |
July 24, 2007 |
| Differential amplifier includes a differential amplifier circuit, a bias circuit and an output circuit. The differential amplifier circuit includes first and second differential amplifier sections. The first differential amplifier section includes a first PMOS transistor which has a |
| 7248078 |
Semiconductor device |
July 24, 2007 |
| The semiconductor device according to the present invention comprises an output MOS transistor M0, an MOS transistor M3 connected between a gate G1 of the output MOS transistor M0 and a ground voltage GND, a parasitic transistor Tr1 which is formed in parallel with the MOS transistor M3 |
| 7248025 |
Voltage regulator with improved power supply rejection ratio characteristics and narrow response |
July 24, 2007 |
| In a voltage regulator, a reference voltage generating circuit generates a reference voltage. A drive transistor is connected between a first power supply terminal and an output terminal and has a control terminal. A voltage divider generates a feedback voltage which is an intermediate |
| 7247935 |
Semiconductor device |
July 24, 2007 |
| A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical |
| 7247904 |
Semiconductor device memory cell |
July 24, 2007 |
| A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back |
| 7246052 |
Bus master and bus slave simulation using function manager and thread manager |
July 17, 2007 |
| The system simulator comprises master simulators 1f, 1s, 2f and 2s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially actuating the master simulator and the slave simulator by using a function call and a thread manager S for |
| 7245872 |
Satellite broadcasting converter, control circuit incorporated therein, and detector circuit use |
July 17, 2007 |
| In a broadcasting satellite converter adapted to be connected to a BS tuner and fed with a power supply voltage signal from the broadcasting satellite tuner, a receiver circuit is controlled by a control circuit. The broadcasting satellite converter comprises a receiver circuit inclu |
| 7245155 |
Data output circuit with improved overvoltage/surge protection |
July 17, 2007 |
| A data output circuit is composed of first and second differential MOS transistors, first and second cascade MOS transistors, first and second outputs, and first and second resistor elements. The first and second differential MOS transistors receive first and second input voltages on |
| 7245146 |
Semiconductor device with termination resistance adjusting circuit |
July 17, 2007 |
| A semiconductor device includes a transmitter, a termination resistance adjusting section, a transmitter control section and a control signal generating section. The transmitter has two output terminals and operates based on a control current. The termination resistance adjusting section |
| 7244986 |
Two-bit cell semiconductor memory device |
July 17, 2007 |
| A 2-bit cell is made up of first and second diffusion regions provided on a substrate surface, first and second storage nodes adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second storage nodes, a third storage node provided on t |
| 7243180 |
Semiconductor memory device with bus driver circuit configured to transfer an output on a common |
July 10, 2007 |
| A semiconductor memory device includes first to third data buses, and first and second connection circuits. The first connection circuit inverts and transfers a first output signal on the first data bus read out from a memory onto the second data bus in response to a first selection |
| 7242093 |
Semiconductor device |
July 10, 2007 |
| The present invention provides a large scale integrated circuit which is capable of coping with the problems associated with the situation in which the number of pins used in the circuit is increased, and is capable, even when dummy bumps (DBPs) are installed, of suppressing storage |
| 7242085 |
Semiconductor device including a semiconductor chip mounted on a metal base |
July 10, 2007 |
| A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portion |
| 7239538 |
Semiconductor storage device |
July 3, 2007 |
| The SRAM cell 1 includes inverters 10, 20, N-type FETs (Field Effect Transistors) 32, 34, 36, 38, word lines 42, 44, and bit lines 46, 48. A gate width W2 and gate length L2 of the FETs 32, 34, 36, 38 are equal to a gate width W3 and gate length L3 of the FETs 12, 22, respectively. In |
| 7239495 |
Output circuit with transistor overcurrent protection |
July 3, 2007 |
| When the overcurrent detection circuit detects that a voltage drop of the output transistor exceeds a threshold value, it turns on the switch by the first operational amplifier. In the shut-down signal generation circuit, the capacitor is charged with a charge current determined based |
| 7239218 |
Phase shifter having switchable high pass filter and low pass filter paths and impedance adjustm |
July 3, 2007 |
| A phase shifter with a low insertion loss in which impedance mismatch at a point in rear of a high-pass filter or a low-pass filter in the signal flow direction is reduced and difference in insertion loss or phase shifting error across a high-pass filter- low-pass filter is suppressed. |
| 7239190 |
Clock control method and circuit |
July 3, 2007 |
| A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first an |
| 7239189 |
Clock generating circuit |
July 3, 2007 |
| A clock generating circuit includes a first delay circuit array, which has a plurality of delay circuits, for measuring delay of an input signal, and a second delay circuit array for delay-replay having a plurality of delay circuits and being arranged in a direction opposite a direction |
| 7239007 |
Bipolar transistor with divided base and emitter regions |
July 3, 2007 |
| A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spa |
| 7239002 |
Integrated circuit device |
July 3, 2007 |
| In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An insulating layer i |
| 7238996 |
Semiconductor device |
July 3, 2007 |
| A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high |
| 7238992 |
Semiconductor circuit for DC-DC converter |
July 3, 2007 |
| In a semiconductor integrated circuit for a DC--DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other |
| 7238980 |
Semiconductor device having plural electroconductive plugs |
July 3, 2007 |
| The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. |
| 7238548 |
Flip-chip type semiconductor device, production process for manufacturing such flip-chip type se |
July 3, 2007 |
| A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrod |
| 7236373 |
Electronic device capable of preventing electromagnetic wave from being radiated |
June 26, 2007 |
| A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed |
| 7236042 |
Fuse trimming circuit |
June 26, 2007 |
| To prevent blowing of a fuse resistor due to application of static electricity to a trimming pad. In a fuse trimming circuit capable of switching the input level of a CMOS input circuit by supplying a voltage or a current to a trimming pad so as to blow a fuse resistor, a P-channel M |
| 7236039 |
Spread spectrum clock generating apparatus |
June 26, 2007 |
| Disclosed is a spread spectrum clock generator comprising a phase interpolator, which receives a clock signal from a clock input terminal and a control signal (an up signal and/or down signal), for adjusting the phase of an output clock signal in accordance with said control signal a |
| 7235860 |
Bipolar transistor including divided emitter structure |
June 26, 2007 |
| A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electrically isolated and spa |
| 7235309 |
Electronic device having external terminals with lead-free metal thin film formed on the surface |
June 26, 2007 |
| A resin sealed IC has a plurality of external terminals. A metal thin film made of a Sn--Bi alloy is formed in direct contact with the surface of a base member of each external terminal. A Bi content in the Sn--Bi alloy layer is within a range of 0.5 to 6.0 wt %. Further, the Sn--Bi allo |
| 7233466 |
Input protection circuit |
June 19, 2007 |
| An input protection circuit includes an inverting amplifier circuit which converts the potential of an input signal input in such a way that the potential of the input signal lies in the input range of the potential range of a signal inputtable to an IC internal circuit. One protection |
| 7233152 |
Short detection circuit and short detection method |
June 19, 2007 |
| A circuit and method for judging a latent short-circuit defect, also known as a short-circuit defect with time passing, in the case of a high voltage system. A detection-dedicated wiring for detecting a short-circuit defect is provided between a first high voltage system wiring and a |
| 7233066 |
Multilayer wiring substrate, and method of producing same |
June 19, 2007 |
| A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer |
| 7230493 |
Bias circuit with threshold voltage change compensation function and temperature change compensa |
June 12, 2007 |
| A bias circuit which applies a bias voltage to a control terminal of a first active element for an RF signal amplification, includes a threshold voltage change compensation circuit and a first temperature compensation circuit. The threshold voltage change compensation circuit contains a |
| 7230446 |
Semiconductor logic circuit device having pull-up/pull-down circuit for input buffer pad and waf |
June 12, 2007 |
| In a semiconductor logic circuit device including an internal circuit, a group of first pads, a group of second pads, and a plurality of input buffers, each connected between the internal circuit and one of the first and second pads, for supplying input signals from their corresponding |
