| Patent Number |
Title Of Patent |
Date Issued |
| 7149555 |
Mobile phone capable of stopping main clock signal |
December 12, 2006 |
| A mobile phone has at least one main clock system and operating based on a main clock signal of the main clock system. The main clock system includes a main counter for counting main clocks of the main clock signal; and a power saving section for stopping generation of the main clock |
| 7148724 |
Signal output circuit |
December 12, 2006 |
| The signal output circuit 1 includes a first and a second emitter follower circuit, and a comparator 20. The comparator 20 receives output signals from the first and the second emitter follower circuit, and outputs a result of comparison in magnitude between those signals. The comparator |
| 7148575 |
Semiconductor device having bonding pad above low-k dielectric film |
December 12, 2006 |
| A semiconductor device comprises a protective element on a substrate; a low-k dielectric film opposite the protective element and having mechanical strength smaller than a silicon oxide film; a mesh wiring opposite the protective element and in the low-k dielectric film, the mesh wir |
| 7148571 |
Semiconductor device and method of manufacturing the same |
December 12, 2006 |
| Provided is a semiconductor device comprising: an HSQ layer formed on a Cu wiring line and having properties that Cu is unlikely to enter the HSQ layer; a plug formed in the HSQ layer and connected to the Cu wiring line; and a Cu wiring line inserted inside the HSQ layer and connected to |
| 7146549 |
Scan-path flip-flop circuit for integrated circuit memory |
December 5, 2006 |
| A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to |
| 7145830 |
Semiconductor memory device |
December 5, 2006 |
| A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in |
| 7145812 |
Semiconductor memory device and method of entry of operation modes thereof |
December 5, 2006 |
| There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.If read cycles for plural addresses are continued, then a request for entry of |
| 7145247 |
Offset-bonded, multi-chip semiconductor device |
December 5, 2006 |
| The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one |
| 7145230 |
Semiconductor device with a solder creep-up prevention zone |
December 5, 2006 |
| The present invention provides a semiconductor device which includes a U-shaped metal package base, and a semiconductor chip having at least surface electrodes and being mounted on the inner bottom portion of the U-shaped metal package base, wherein the metal package base has, in a p |
| 7143229 |
Single-chip microcomputer with dynamic burn-in test function and dynamic burn-in testing method |
November 28, 2006 |
| In a single-chip microcomputer including a nonvolatile semiconductor memory device and write, read and erase circuits for performing a write operation, a read operation and an erase operation upon the nonvolatile semiconductor memory device, respectively, a sequencer is connected bet |
| 7139286 |
Method and system for insertion and extraction of overhead in SONET/SDH |
November 21, 2006 |
| An overhead insertion interface unit connected to a high-speed line via a frame processing unit includes a TOH FIFO, a POH FIFO, and a common gate for transmitting a TOH input request and a POH input request to an external device. Each of the FIFOs receives a TOHAV signal together with |
| 7139186 |
Failure detection circuit |
November 21, 2006 |
| A failure detection circuit that can detect the performance degradation of a FeRAM caused by thermal stress regardless of whether power is being supplied or not, and prevent the use of a deteriorated FeRAM. It comprises a detector FeRAM cell structured identically to a memory cell ac |
| 7138866 |
Operational amplifier including low DC gain wideband circuit and high DC gain narrowband gain ci |
November 21, 2006 |
| In an operational amplifier including first and second power supply terminals, first and second input terminals, and first and second output terminals, a first differential amplifier circuit including a first drive cascode circuit and a first tail current source amplifies first and s |
| 7138817 |
Method and apparatus for testing defective portion of semiconductor device |
November 21, 2006 |
| An apparatus for testing a defect, includes a semiconductor element. In the semiconductor element, a conductive film is formed on an STI (shallow trench isolation) insulating film, which fills a shallow trench extending into a semiconductor region, opposing said semiconductor region thro |
| 7138700 |
Semiconductor device with guard ring for preventing water from entering circuit region from outs |
November 21, 2006 |
| A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first |
| 7138673 |
Semiconductor package having encapsulated chip attached to a mounting plate |
November 21, 2006 |
| In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. Th |
| 7138362 |
Washing liquid composition for semiconductor substrate |
November 21, 2006 |
| There is provided a washing liquid composition for a semiconductor substrate having a contact angle between the surface thereof and water dropped thereon of at least 70 degrees, the washing liquid composition including an aliphatic polycarboxylic acid and a surfactant, and the washin |
| 7138064 |
Semiconductor device and method of manufacturing the same |
November 21, 2006 |
| The present invention relates to a method of manufacturing a semiconductor device. In the method, an etching-back layer consisting of aluminum or copper is formed on a base substrate and a multilayer wiring board is manufactured on the etching-back layer. After that the etching-back laye |
| 7136771 |
Semiconductor device and testing circuit which can carries out a verifying test effectively for |
November 14, 2006 |
| A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. The first logical pr |
| 7135937 |
Oscillator circuit and integrated circuit incorporating the same |
November 14, 2006 |
| The oscillator circuit comprises a capacitor and first to fourth constant current supplies and switches are connected to the capacitor. Both terminals of the capacitor are used for charges and discharges. One period comprises four steps; charging the first terminal of the capacitor, |
| 7135776 |
Semiconductor device and method for manufacturing same |
November 14, 2006 |
| A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 1 |
| 7135739 |
Vertical-type metal insulator semiconductor field effect transistor device, and production metho |
November 14, 2006 |
| In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type sourc |
| 7135717 |
Semiconductor switches and switching circuits for microwave |
November 14, 2006 |
| The purpose of the present invention is to provide a small-sized switch attaining high isolation of not less than 80 dB, maintaining low insertion loss also in high frequencies not less than 60 GHz. A semiconductor switch according to the present invention utilizes FETs a gate electr |
| 7134111 |
Layout method and apparatus for arrangement of a via offset from a center axis of a conductor an |
November 7, 2006 |
| A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is provided in an interconnect layer different from the interconnect layer of the first conducto |
| 7132732 |
Semiconductor device having two distinct sioch layers |
November 7, 2006 |
| A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a firs |
| 7129882 |
Successive approximation ad converter having pulse noise suppression |
October 31, 2006 |
| A successive approximation AD converter. A voltage comparator receives an analog input signal and a reference voltage. A successive approximation register receives the voltage comparator output, and a DA converter, connected to the successive approximation register, provides another |
| 7129773 |
Band-gap type constant voltage generating circuit |
October 31, 2006 |
| A band-gap type constant voltage generating circuit is produced in a semiconductor chip, and has a first potential terminal and a second potential terminal. A band-gap circuit includes first and second transistors having respective bases connected to each other, a first resistor conn |
| 7129759 |
Integrated circuit including an overvoltage protection circuit |
October 31, 2006 |
| The power IC includes an output transistor M0 which controls a current flowing into an L load, a dynamic clamp circuit which clamps an overvoltage, and a clamp control circuit which controls the operation of the dynamic clamp circuit. The clamp control circuit activates the dynamic c |
| 7126522 |
Apparatus and method of analog-to-digital conversion |
October 24, 2006 |
| An analog-to-digital conversion apparatus includes a register group, a selecting section and an A/D conversion section. The register group has a plurality of registers holding a plurality of channel specification data, respectively. The selecting section is connected with a plurality of |
| 7126508 |
Analog-to-digital conversion system, correction circuit, and correction method |
October 24, 2006 |
| Disclosed is an interleaved ADC comprising first and second component ADCs that use pipelined ADCs extracts an image component, which is generated by a gain error, with the use of a band pass filter for correcting the gain error so that the power of the image component is minimized. |
| 7126191 |
Double-diffused semiconductor device |
October 24, 2006 |
| A DMOSFET and a method of fabricating the same, capable of keeping a desirable level of drain voltage resistance and, at the same time, of reducing the drain resistance. In a DMOSFET configured as having a drain region composed of an epitaxial layer formed on a P-type semiconductor s |
| 7125765 |
Semiconductor device and method for manufacturing same |
October 24, 2006 |
| A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of Al.sub.XZr.sub.(1-X)O.sub.Y (0.05.ltoreq.X.ltoreq.0.3), |
| 7124311 |
Method for controlling processor in active/standby mode by third decoder based on instructions s |
October 17, 2006 |
| In a system large scale integrated circuit (LSI) according to one embodiment, management of the power supply, and the like, of a dedicated instruction processor can be carried out according to an instruction issued to a basic instruction processor at high speed. Further, the operatio |
| 7123514 |
Memory device for improved reference current configuration |
October 17, 2006 |
| A memory device is composed of a memory array including floating gate memory cells; a sense amplifier designed to identify data stored in the memory array; and a reference current setting unit responsive to a trimming code for providing a reference current for the sense amplifier. Th |
| 7122912 |
Chip and multi-chip semiconductor device using thereof and method for manufacturing same |
October 17, 2006 |
| The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing same are presented, w |
| 7122902 |
Semiconductor device |
October 17, 2006 |
| A semiconductor device according to the present invention comprises a substrate; a copper interconnect layer formed on the top surface side of the substrate; an aluminum bonding pad formed on the top surface side of the copper interconnect layer with an aluminum-based material; and an |
| 7120891 |
Master slice semiconductor integrated circuit |
October 10, 2006 |
| It is an object of the present invention to reduce power consumption and improve flexibility in a master slice semiconductor integrated circuit. The master slice semiconductor integrated circuit comprises at least two wiring layers to form wirings, and a plurality of clock buffers connec |
| 7120829 |
Failure propagation path estimate system |
October 10, 2006 |
| The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-ca |
| 7119782 |
Display device and driving method of the same |
October 10, 2006 |
| A display device is provided with a display controller, a source driver, and a liquid crystal panel, and two pairs of wirings are provided between the display controller and the source driver. The display controller is provided with a V-I conversion circuit for image data and a mode |
| 7119626 |
Oscillation circuit and operation method thereof |
October 10, 2006 |
| An oscillation circuit has: a first MOS transistor having a gate connected to a first node and a source connected to the ground; a second MOS transistor having a gate connected to a second node and a source connected to the ground; a current supply circuit supplying a control current |
| 7119599 |
Clock control circuit and method |
October 10, 2006 |
| A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 11.sub.1 |
| 7119598 |
Clock control circuit and method |
October 10, 2006 |
| A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 11.sub.1 |
| 7119441 |
Semiconductor interconnect structure |
October 10, 2006 |
| In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu dif |
| 7118835 |
Semiconductor device and method of forming the same as well as a photo-mask used therein |
October 10, 2006 |
| A method of forming a device pattern of a semiconductor device. The method includes the steps of carrying out an over-exposure to a resist film using a mask which has transmission regions which are positioned about a circumference of each of intended patterns of a resist film. Then c |
| 7116581 |
Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor m |
October 3, 2006 |
| A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program |
| 7113156 |
Driver circuit of display device |
September 26, 2006 |
| It has a gradation voltage generation circuit 1 for generating a plurality of voltage values suited to gamma characteristics of a liquid crystal and so on, a digital image data storage circuit 3 for storing digital image data displayed on a display device, a gradation voltage selection c |
| 7112852 |
Semiconductor device |
September 26, 2006 |
| The electrostatic protection device provided between an input/output terminal and an internal circuit of a semiconductor device according to the present invention has a first insulated gate field effect transistor (MOS transistor) and a second MOS transistor that are connected mutually |
| 7109769 |
PWM signal generator |
September 19, 2006 |
| A PWM signal generator comprises a pulse width indication signal generator outputting a pulse width indication signal, and a pulse width adjustment portion receiving the pulse width indication signal. The pulse width adjustment portion outputs an adjusted pulse width data which correspon |
| 7109533 |
Electrostatic discharge protection device |
September 19, 2006 |
| There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery |
| 7106144 |
Semiconductor integrated circuit |
September 12, 2006 |
| An oscillating section 110 comprised of feedback inverter INV1 and a feedback resistor R2, and a waveform shaping section 120 including a Schmitt circuit S1 of which transistors P3 and N3 respectively receive, as gate control signals, signals Gp3 and Gn3 generated by a stable-oscilla |
