| Patent Number |
Title Of Patent |
Date Issued |
| 7436450 |
Linear image sensor |
October 14, 2008 |
| A linear image sensor, comprises a first and second gate/shutter arrays in which a plurality of the read gates and of the shutter structure sections are alternately disposed, a light-receiving element array which is disposed between the first and second gate/shutter arrays and in which a |
| 7436069 |
Semiconductor device, having a through electrode semiconductor module employing thereof and meth |
October 14, 2008 |
| The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A plurality of columnar through plugs 107 are pr |
| 7435948 |
Adherence of a solid-state image-sensing device to a substrate |
October 14, 2008 |
| To provide a solid-state image sensing device that is capable of improving the connection reliability of bonding pads and bonding wires. A solid-state image sensing element 1 of the present invention contains a long plate-shaped metal substrate 16, a long plate-shaped solid-state ima |
| 7435649 |
Floating-gate non-volatile memory and method of fabricating the same |
October 14, 2008 |
| A floating gate non-volatile memory is composed of a semiconductor substrate within which active regions and isolation dielectrics are alternately arranged in a first direction; a word line extending in the first direction to intersect with the active regions and the isolation dielec |
| 7433793 |
Error detection apparatus and method and signal extractor |
October 7, 2008 |
| A modulated voltage signal modulated at a predetermined frequency f0 is supplied to an integrated circuit under test to be tested set at an arbitrary stationary point, and an observation signal containing information on power supply current flowing through the integrated circuit unde |
| 7432903 |
Common inversion driving type liquid crystal display device and its driving method capable of su |
October 7, 2008 |
| In a method for driving a common inversion type liquid crystal display apparatus including a plurality of signal lines, a plurality of scan lines, a common electrode, and a plurality of pixel units, a common voltage applied to the common electrode is inverted for every scan line. Als |
| 7432597 |
Semiconductor device and method of manufacturing the same |
October 7, 2008 |
| In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in a |
| 7432588 |
Semiconductor device and method of fabricating the same |
October 7, 2008 |
| A semiconductor device 100 comprises a leadframe 104 having an island portion 102; two chips of a first semiconductor chip 110 and a second semiconductor chip 120, respectively having top surfaces having, in the peripheral areas thereof, pad portions respectively having a plurality of |
| 7432551 |
SOI semiconductor device including a guard ring region |
October 7, 2008 |
| An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI |
| 7432545 |
Semiconductor device |
October 7, 2008 |
| A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is |
| 7432170 |
Semiconductor device and fabrication method thereof |
October 7, 2008 |
| On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor- |
| 7432169 |
Method for manufacturing semiconductor device |
October 7, 2008 |
| An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom of a trench formed in a P |
| 7432134 |
Semiconductor device and method of fabricating the same |
October 7, 2008 |
| A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming region and having an element-isolating region 118 formed therein. On the main surface of the s |
| 7429854 |
CMOS current mirror circuit and reference current/voltage circuit |
September 30, 2008 |
| Disclosed is a CMOS current mirror circuit including a first MOS transistor and a second MOS transistor constituting a current mirror, in which a drain of the first MOS transistor and a gate of the second MOS transistor are connected in common, a source of the first MOS transistor is |
| 7429768 |
Semiconductor device having a trench surrounding each of plural unit cells |
September 30, 2008 |
| A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and se |
| 7428676 |
Boundary scan device |
September 23, 2008 |
| A boundary-scan device in which a plurality of signal paths are connected to the macro, each having a data signal input end and a data signal output end for signal transmission during normal mode operations. A plurality of circuits is provided for the plurality of signal paths, respe |
| 7428608 |
Communication system, communication circuit and communication method |
September 23, 2008 |
| A communication system according to an embodiment of the invention includes: a plurality of communication nodes; and a common bus connected with the plurality of communication nodes, wherein the plurality of communication nodes individually checks a use state of the bus to allow/disa |
| 7427892 |
Current source circuit and method of outputting current |
September 23, 2008 |
| A current source circuit includes a voltage output section which outputs a voltage signal; a current source section and a conversion section. The current source section has at least one current source block comprising a plurality of current sources, each of which outputs an output curren |
| 7427880 |
Sample/hold apparatus with small-sized capacitor and its driving method |
September 23, 2008 |
| A sample/hold apparatus includes first, second and third power supply terminals to which first, second and third power supply voltages are applied. The second power supply voltage is an intermediate voltage between are first and third power supply voltages. A sampling switching eleme |
| 7426368 |
Satellite broadcasting converter, control circuit incorporated therein, and detector circuit use |
September 16, 2008 |
| In a broadcasting satellite converter adapted to be connected to a BS tuner and fed with a power supply voltage signal from the broadcasting satellite tuner, a receiver circuit includes a mixer, and a plurality of local oscillators connected to the mixer to convert broadcasting satel |
| 7425733 |
Semiconductor apparatus with electrostatic protective device |
September 16, 2008 |
| A semiconductor apparatus includes an electrostatic protective device having PN junction with N-type Si and P-type SiGe. The electrostatic protective device is directly connected with a terminal to receive static electricity and with a terminal to discharge static electricity. |
| 7421631 |
Semiconductor device with termination resistor circuit |
September 2, 2008 |
| A semiconductor device includes a signal line, a test load circuit and a termination circuit. The signal line is connected with an input/output node of the semiconductor device. The test load circuit has a test resistor and is provided between the signal line and a first one of power |
| 7420495 |
Current source cell arrangement and digital-to-analog converter |
September 2, 2008 |
| An object of the present invention is to form a highly accurate current source for D/A converters. Letters from a.sub.1 to a.sub.n where n is at least 4 represent current source cells that output constant currents, each of which is composed of MOS transistors etc. These current source |
| 7420410 |
Variable gain amplifier circuit, method of correcting DC offset of the variable gain amplifying |
September 2, 2008 |
| A variable gain amplifier circuit according to an embodiment of the invention includes: an output offset correcting unit for executing correction to attenuate a fixed offset component independent of a gain change of a variable gain amplifier circuit out of a DC offset involved in an |
| 7420279 |
Carbon containing silicon oxide film having high ashing tolerance and adhesion |
September 2, 2008 |
| An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si--CH2 bond therein. The proportion of Si--CH2 bond (1360 cm-1) to Si--CH3 |
| 7420190 |
Length measurement pattern, semiconductor device, and method of manufacturing a semiconductor de |
September 2, 2008 |
| A length measurement pattern is used for forming a contact and a via on a diffusion layer and on a lower layer interconnect, respectively, with a photoresist. The length measurement pattern includes a first pattern 16 serving as an object of length measurement in length measurement SEM a |
| 7419767 |
Phase-shifting mask and method of forming pattern using the same |
September 2, 2008 |
| A phase-shifting mask suppresses increase of the minimum pattern-element size due to optical proximity effect. The mask a first pattern region formed on a transparent substrate, including a first blocking part for forming at least one first pattern element. The mask further includes a |
| 7417915 |
Multiport memory device |
August 26, 2008 |
| A multiport memory device according to an embodiment of the invention includes first and second input ports, first and second output ports, and a memory cell array. The device further includes: an input data selector for selecting one of the first and second input ports to send input dat |
| 7417487 |
Overheat detecting circuit |
August 26, 2008 |
| An overheat detecting circuit according to an embodiment of the invention includes: a current source for generating a constant current; an overheat detecting element unit that operates with a first current generated in accordance with the constant current and generates a first voltage ba |
| 7417438 |
Battery voltage measurement apparatus |
August 26, 2008 |
| A voltage measurement circuit includes a plurality of voltage input terminals that are supplied with voltage outputted by secondary batteries via voltage measurement lines, a plurality of voltage sensors connected between each of the plurality of voltage input terminals; and a plurality |
| 7417324 |
Semiconductor device and method for manufacturing the same |
August 26, 2008 |
| A semiconductor device is composed of a semiconductor chip, aluminum pads formed on the semiconductor chip, alloy ball bumps, which are formed on the aluminum pads, containing gold and Pd, and gold wires, which are connected to the alloy ball bumps, having a surface made of gold. The |
| 7417319 |
Semiconductor device with connecting via and dummy via and method of manufacturing the same |
August 26, 2008 |
| An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first |
| 7417277 |
Semiconductor integrated circuit and method of manufacturing the same |
August 26, 2008 |
| Conventional capacitors constituted of a FET incur degradation in frequency response. A semiconductor integrated circuit includes a semiconductor substrate, an N-type FET, a P-type FET, and capacitors. The N-type FET includes N-type impurity diffusion layers, a P-type impurity-implan |
| 7414506 |
Semiconductor integrated circuit and fabrication method thereof |
August 19, 2008 |
| A multilayer interconnection layer is provided on a semiconductor substrate. An inductor is provided on an insulating layer that forms the uppermost layer of the multilayer interconnection layer. The inductor is formed by spirally arranging a single wiring. On the insulating layer, a |
| 7411851 |
Semiconductor device |
August 12, 2008 |
| A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as |
| 7411838 |
Semiconductor memory device |
August 12, 2008 |
| A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the voltag |
| 7411256 |
Semiconductor integrated circuit device capacitive node interconnect |
August 12, 2008 |
| A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliability in the node inte |
| 7409648 |
Semiconductor integrated circuit, method for designing semiconductor integrated circuit and syst |
August 5, 2008 |
| The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic o |
| 7408402 |
Operational amplifier with less offset voltage |
August 5, 2008 |
| An operational amplifier includes a differential pair section; a load section configured to function as active load of the differential pair section; and a switch section configured to switch supply of a differential input signal to the differential pair section and to switch connect |
| 7408387 |
Output buffer circuit with control circuit for changing resistance of output resistor pair |
August 5, 2008 |
| Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential inp |
| 7408315 |
Motor control apparatus, motor control circuit, and method thereof |
August 5, 2008 |
| A motor control apparatus for controlling a motor based on an output from a sensor includes a storage unit storing a value according to an excitation power supply to excite the sensor, a PWM output unit outputting a PWM output signal having a pulse width modulated to have a duty rati |
| 7407880 |
Semiconductor device and manufacturing process therefore |
August 5, 2008 |
| A semiconductor device which can prevent a leak current between a silicide layer on a polysilicon and another part, as well as a manufacturing process therefor. The semiconductor device includes neighboring n- and p-type polysilicons; and a silicide layer thereon extending from the n |
| 7406145 |
Jitter detection circuit |
July 29, 2008 |
| There is provided a jitter detection circuit of a phase locked loop circuit, comprising a comparison circuit. The comparison circuit compares an input clock that is inputted to the phase locked loop circuit and an output clock that is outputted by the phase locked loop circuit. When it |
| 7405976 |
Nonvolatile semiconductor memory and method for controlling the same |
July 29, 2008 |
| A nonvolatile semiconductor memory includes a memory cell array, a flag information storage that stores a write flag indicating success/failure of writing in association with each address of a plurality of data segments contained in the data block, an internal address storage that se |
| 7405958 |
Magnetic memory device having XP cell and Str cell in one chip |
July 29, 2008 |
| According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MRAM cell array serves a |
| 7405622 |
Operational amplifier with less offset |
July 29, 2008 |
| A differential amplifier includes an input stage circuit including a first differential pair and a second differential pair which are complementary to each other; a first current mirror circuit connected with the first differential pair and configured to function as an active load; a sec |
| 7405472 |
Semiconductor device |
July 29, 2008 |
| A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical |
| 7403037 |
Signal amplifier |
July 22, 2008 |
| The signal amplifier has a source follower receiving an input signal, a voltage divider generating a bias voltage which is input to the source follower through a different path from the input signal, and an inverter connected in series in the subsequent stage of the source follower and |
| 7402914 |
Semiconductor device featuring overlay-mark used in photolithography process |
July 22, 2008 |
| In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper mask element formed |
| 7402867 |
Semiconductor device |
July 22, 2008 |
| In a semiconductor device, a plurality of first diffusion regions of a first conductive type are formed on a diffusion layer well of the first conductive type. A plurality of second diffusion regions of a second conductive type are formed on the diffusion layer well of the first cond |
