| Patent Number |
Title Of Patent |
Date Issued |
| 7432204 |
Wafer and the manufacturing and reclaiming methods thereof |
October 7, 2008 |
| A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having a semiconductor s |
| 7402522 |
Hard mask structure for deep trenched super-junction device |
July 22, 2008 |
| A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for block |
| 7375005 |
Method for reclaiming and reusing wafers |
May 20, 2008 |
| Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semiconductor substrate; |
| 7358168 |
Ion implantation method for forming a shallow junction |
April 15, 2008 |
| A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implantation method for form |
| 7344998 |
Wafer recovering method, wafer, and fabrication method |
March 18, 2008 |
| In order to use an etching solution of less complicated composition for recovering used wafers, embodiments of the present invention provide a recovering method, and also provide a kind of wafer, which is used as a process control wafer or dummy wafer, and fabrication methods. In one |
| 7282429 |
Method of manufacturing Schottky diode device |
October 16, 2007 |
| Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing the polysilicon layer t |
| 7271048 |
Method for manufacturing trench MOSFET |
September 18, 2007 |
| A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically |
| 7265024 |
DMOS device having a trenched bus structure |
September 4, 2007 |
| A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a |
| 7211523 |
Method for forming field oxide |
May 1, 2007 |
| A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substrate in a region not |
| 7205196 |
Manufacturing process and structure of integrated circuit |
April 17, 2007 |
| The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultane |
| 7192789 |
Method for monitoring an ion implanter |
March 20, 2007 |
| A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion implantation process to |
| 7126853 |
Electronic memory having impedance-matched sensing |
October 24, 2006 |
| An electronic memory, typically a flash EPROM, contains an array of memory sections (40), each containing an array of memory cells (54). Global bit lines (60) fully traverse the memory. Local bit lines (58) partially traverse the memory. Data stored in the memory is sensed with an ar |
| 7118971 |
Method for fabricating trench power device |
October 10, 2006 |
| Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, |
| 7118778 |
Method of applying adhesive |
October 10, 2006 |
| An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust pipe, so as to have th |
| 7092836 |
Method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device |
August 15, 2006 |
| A method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system is introduced to screen the complicated wiring state of the hi-fix structure and to pinpoint the wiring swap thereinside as well. The hi-fix structure has at least S socket s |
| 7087958 |
Termination structure of DMOS device |
August 8, 2006 |
| In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide |
| 7084457 |
DMOS device having a trenched bus structure |
August 1, 2006 |
| A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a |
| 7070484 |
Pad break-in method for chemical mechanical polishing tool which polishes with ceria-based slurr |
July 4, 2006 |
| A chemical mechanical polishing (CMP) method is disclosed in which a new polishing pad is broken-in and conditioned into a steady operating state while using a silica (SiO.sub.2) based CMP slurry and where the broken-in and conditioned pad is afterwards used for polishing patterned workp |
| 7047620 |
Method for assembling a scrubber |
May 23, 2006 |
| The present invention relates to a method of assembling a scrubber which includes a motor, a shaft rotatably coupled to and extending through the motor, a shaft pin detachably connected to the shaft, and a disk coupled to the shaft and having a notch located relative to the shaft pin at |
| 7046551 |
Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines e |
May 16, 2006 |
| Nonvolatile memory cells (110) are connected to a bitline (BL 170). The bitline is also connected to a source/drain region (620) of a transistor (610), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher |
| 7045435 |
Shallow trench isolation method for a semiconductor wafer |
May 16, 2006 |
| The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing pheno |
| 7040958 |
Torque-based end point detection methods for chemical mechanical polishing tool which uses ceria |
May 9, 2006 |
| A chemical mechanical polishing (CMP) method is disclosed in which a torque-based end-point algorithm is used to determine when polishing should be stopped. The end-point algorithm is applicable to situations where a ceria (CeO.sub.2) based CMP slurry is used for further polishing, p |
| 7015112 |
Method of forming bottom oxide layer in trench structure |
March 21, 2006 |
| Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PECVD process with TEOS |
| 7004012 |
Method of estimating thickness of oxide layer |
February 28, 2006 |
| Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an |
| 6998315 |
Termination structure for trench DMOS device and method of making the same |
February 14, 2006 |
| Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, th |
| 6997788 |
Multi-tool, multi-slurry chemical mechanical polishing |
February 14, 2006 |
| A chemical mechanical polishing method is disclosed in which a batch of wafers is first supplied to a low-selectivity, first CMP tool for partly polishing the batch with one or more relatively non-selective CMP slurries (e.g., silica (SiO.sub.2) based); and in which the batch of part |
| 6991994 |
Method of forming rounded corner in trench |
January 31, 2006 |
| A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first |
| 6989306 |
Termination structure of DMOS device and method of forming the same |
January 24, 2006 |
| Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then sele |
| 6984574 |
Cobalt silicide fabrication using protective titanium |
January 10, 2006 |
| A cobalt silicide fabrication process entails first depositing a cobalt layer (120) on a silicon-containing EPROM region. A titanium layer (130) is formed over the cobalt layer by ionized physical vapor deposition ("IPVD") to protect the cobalt layer from contaminant gases. Cobalt of |
| 6975535 |
Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage |
December 13, 2005 |
| A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the |
| 6974749 |
Bottom oxide formation process for preventing formation of voids in trench |
December 13, 2005 |
| Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a trench structure co |
| 6958276 |
Method of manufacturing trench-type MOSFET |
October 25, 2005 |
| In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage in the partial sem |
| 6955987 |
Comparison of chemical-mechanical polishing processes |
October 18, 2005 |
| Chemical-mechanical polishing ("CMP") processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulat |
| 6933218 |
Low temperature nitridation of amorphous high-K metal-oxide in inter-gates insulator stack |
August 23, 2005 |
| An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal |
| 6916126 |
Developing method for semiconductor substrate |
July 12, 2005 |
| Embodiments of the present invention provide a developing method, which can efficiently prevent the developing solution from remaining on the backside surface of the wafer, so as to avoid the influence of the contamination on the subsequent processes. In one embodiment, a developing meth |
| 6893921 |
Nonvolatile memories with a floating gate having an upward protrusion |
May 17, 2005 |
| In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the |
| 6888197 |
Power metal oxide semiconductor field effect transistor layout |
May 3, 2005 |
| A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is |
| 6880382 |
Leakage detecting method for use in oxidizing system of forming oxide layer |
April 19, 2005 |
| Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing system of forming an |
| 6875085 |
Polishing system including a hydrostatic fluid bearing support |
April 5, 2005 |
| A polishing system such as a chemical mechanical belt polisher includes a hydrostatic fluid bearing that supports polishing pads and incorporates one or more of the following novel aspects. One aspect uses compliant surfaces surrounding fluid inlets in an array of inlets to extend areas |
| 6864148 |
Corner protection to reduce wrap around |
March 8, 2005 |
| A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. |
| 6859754 |
Statistical process control method and system thereof |
February 22, 2005 |
| A statistical process control (SPC) method, wherein a post-stage process corresponds to a pre-stage process, is disclosed in the present invention. In one embodiment, the SPC method comprises: collecting a plurality of pre-stage measurements and post-stage measurements respectively durin |
| 6855986 |
Termination structure for trench DMOS device and method of making the same |
February 15, 2005 |
| Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, th |
| 6826822 |
Method for preparing rubber plate used in an ion implanter |
December 7, 2004 |
| One embodiment is directed to a method for trimming a rubber plate which is configured to be placed on a platform of an ion implanter, wherein the platform of the ion implanter includes a plurality of primary holes and a plurality of primary notches. The method comprises providing a temp |
| 6821913 |
Method for forming dual oxide layers at bottom of trench |
November 23, 2004 |
| Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defin |
| 6821847 |
Nonvolatile memory structures and fabrication methods |
November 23, 2004 |
| To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control |
| 6815760 |
Nonvolatile memory structures and fabrication methods |
November 9, 2004 |
| To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control |
| 6812148 |
Preventing gate oxice thinning effect in a recess LOCOS process |
November 2, 2004 |
| Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide lay |
| 6794303 |
Two stage etching of silicon nitride to form a nitride spacer |
September 21, 2004 |
| A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fl |
| 6787914 |
Tungsten-based interconnect that utilizes thin titanium nitride layer |
September 7, 2004 |
| An interconnect for a substructure having an opening (470) with a rounded perimetrical top edge (480) includes a titanium nitride layer (150) and a tungsten layer (160). The titanium layer overlies the substructure, extends into the opening, has a substantially columnar grain structure, |
| 6787415 |
Nonvolatile memory with pedestals |
September 7, 2004 |
| Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of row structures (280). Each row structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the row structures before the conductive layer (160 |
