| Patent Number |
Title Of Patent |
Date Issued |
| RE40326 |
Single chip frame buffer and graphics accelerator |
May 20, 2008 |
| A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further co |
| RE40075 |
Method of multi-level storage in DRAM and apparatus thereof |
February 19, 2008 |
| A method of processing data having one of four voltage levels stored in a DRAM cell is comprised of sensing whether or not the data voltage is above or below a voltage level midway between a highest and a lowest of the four levels, setting the voltage on a reference line higher than the |
| RE37641 |
Dynamic random access memory using imperfect isolating transistors |
April 9, 2002 |
| Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storag |
| 7459949 |
Phase detector circuit and method therefor |
December 2, 2008 |
| The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of |
| 7450444 |
High speed DRAM architecture with uniform access latency |
November 11, 2008 |
| A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line |
| 7391247 |
Timing vernier using a delay locked loop |
June 24, 2008 |
| A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control |
| 7385858 |
Semiconductor integrated circuit having low power consumption with self-refresh |
June 10, 2008 |
| A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for lo |
| 7382638 |
Matchline sense circuit and method |
June 3, 2008 |
| A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline |
| 7369451 |
Dynamic random access memory device and method for self-refreshing memory cells |
May 6, 2008 |
| A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal |
| 7362640 |
Apparatus and method for self-refreshing dynamic random access memory cells |
April 22, 2008 |
| A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwri |
| 7353330 |
Method and apparatus for performing repeated content addressable memory searches |
April 1, 2008 |
| A method for reducing the number of cycles required for setting up content addressable memory contexts is disclosed. In particular, the method reduces the number of cycles required for setting up multiple contexts of burst operations, in which each context includes the same data key. Eac |
| 7350137 |
Method and circuit for error correction in CAM cells |
March 25, 2008 |
| A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method includes the |
| 7349513 |
Process, voltage, temperature independent switched delay compensation scheme |
March 25, 2008 |
| A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit |
| 7334093 |
Block programmable priority encoder in a CAM |
February 19, 2008 |
| A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data |
| 7318123 |
Method and apparatus for accelerating retrieval of data from a memory system with cache by reduc |
January 8, 2008 |
| A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main me |
| 7312636 |
Voltage level shifter circuit |
December 25, 2007 |
| A level shifter circuit for converting a logic signal with logic `1` and `0` levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low |
| 7304876 |
Compare circuit for a content addressable memory cell |
December 4, 2007 |
| A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capac |
| 7299330 |
High bandwidth memory interface |
November 20, 2007 |
| This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory |
| 7298637 |
Multiple match detection circuit and method |
November 20, 2007 |
| A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a refere |
| 7286377 |
Dynamic random access memory device and method for self-refreshing memory cells with temperature |
October 23, 2007 |
| A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode |
| 7279956 |
Systems and methods for minimizing static leakage of an integrated circuit |
October 9, 2007 |
| To minimize static leakage of an integrated circuit, a charge pump generates a negative voltage to be applied to a "sleep" transistor cascaded to a logic gate of the integrated circuit. An adaptive leakage controller determines continuously or periodically whether to adjust the negat |
| 7277334 |
Method and apparatus for synchronization of row and column access operations |
October 2, 2007 |
| A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay ci |
| 7269075 |
Method and apparatus for simultaneous differential data sensing and capture in a high speed memo |
September 11, 2007 |
| A differential data sensing and capture circuit, includes a differential input stage circuit for receiving respective ones of said differential data signals and having first and second output nodes. A latch element is provided, having first and second complementary inputs coupled to rece |
| 7266747 |
Error correction scheme for memory |
September 4, 2007 |
| An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, |
| 7263117 |
Dual control analog delay element and related delay method |
August 28, 2007 |
| A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay |
| 7251148 |
Matchline sense circuit and method |
July 31, 2007 |
| A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline |
| 7248531 |
Voltage down converter for high speed memory |
July 24, 2007 |
| A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp |
| 7227766 |
Mismatch-dependent power allocation technique for match-line sensing in content-addressable memo |
June 5, 2007 |
| A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser |
| 7188211 |
Block programmable priority encoder in a CAM |
March 6, 2007 |
| A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data |
| 7155581 |
Method and apparatus for an energy efficient operation of multiple processors in a memory |
December 26, 2006 |
| A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is |
| 7129760 |
Timing vernier using a delay locked loop |
October 31, 2006 |
| A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control |
| 7123056 |
Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines |
October 17, 2006 |
| A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating ske |
| 7116141 |
Frequency-doubling delay locked loop |
October 3, 2006 |
| A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a r |
| 7106732 |
Default route coding |
September 12, 2006 |
| A multi-level lookup table includes a plurality of search levels with each search level including a plurality of subtrees, each subtree representing a plurality of nodes. A search of the multi-level lookup table for an entry corresponding to a search key results in a value stored in an e |
| 7095640 |
Multiple match detection circuit and method |
August 22, 2006 |
| A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a refere |
| 7062601 |
Method and apparatus for interconnecting content addressable memory devices |
June 13, 2006 |
| A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host contr |
| 7043601 |
Priority encoder circuit and method |
May 9, 2006 |
| A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is disclosed. A priority encoder having blocks of multiple match resolver circuits arranged i |
| 7038517 |
Timing vernier using a delay locked loop |
May 2, 2006 |
| A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control |
| 7012850 |
High speed DRAM architecture with uniform access latency |
March 14, 2006 |
| A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line |
| 7006368 |
Mismatch-dependent power allocation technique for match-line sensing in content-addressable memo |
February 28, 2006 |
| A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser |
| 6992950 |
Delay locked loop implementation in a synchronous dynamic random access memory |
January 31, 2006 |
| A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the |
| 6990001 |
Multiple match detection circuit and method |
January 24, 2006 |
| A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a refere |
| 6987682 |
Matchline sense circuit and method |
January 17, 2006 |
| A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. the circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline |
| 6967523 |
Cascaded charge pump power supply with different gate oxide thickness transistors |
November 22, 2005 |
| A cascaded charge pump based power supply for use with low voltage dynamic random access memory (DRAM) includes a charge pump and a non-overlapping clock signal generator. The charge pump circuit has two pump cascades coupled in parallel. Each pump cascade includes a plurality of pump st |
| 6892279 |
Method and apparatus for accelerating retrieval of data from a memory system with cache by reduc |
May 10, 2005 |
| A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main me |
| 6891772 |
High speed DRAM architecture with uniform access latency |
May 10, 2005 |
| A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line |
| 6888731 |
Method and apparatus for replacing defective rows in a semiconductor memory array |
May 3, 2005 |
| A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a |
| 6888730 |
Content addressable memory cell |
May 3, 2005 |
| A content addressable memory (CAM) having a plurality of ternary memory cells, each ternary half cell comprising an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a first well region and the n-type transistors being formed in a second well |
| 6873568 |
Method and apparatus for synchronization of row and column access operations |
March 29, 2005 |
| A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay c |
| 6873532 |
Content addressable memory cell having improved layout |
March 29, 2005 |
| A CAM cell comprises a pair of SRAM cells, each of which comprise a pair of cross coupled inverters for storing a data value and a pair of access devices for accessing a complementary pair of bit lines. The CAM cell ether comprises a pair of compare circuits, each for comparing said data |
