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Micronas USA, Inc. Patents
Assignee:
Micronas USA, Inc.
Address:
Santa Clara, CA
No. of patents:
17
Patents:




Patent Number Title Of Patent Date Issued
7516259 Combined engine for video and graphics processing April 7, 2009
The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration
7432988 Address generation for video processing October 7, 2008
A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a m
7430621 Multiple channel data bus control for video processing September 30, 2008
A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of
7430238 Shared pipeline architecture for motion vector prediction and residual decoding September 30, 2008
A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of
7411628 Method and system for scaling, filtering, scan conversion, panoramic scaling, YC adjustment, and August 12, 2008
Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by re
7408590 Combined scaling, filtering, and scan conversion August 5, 2008
Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce that amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing
7380036 Combined engine for video and graphics processing May 27, 2008
The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration
7376288 Edge adaptive demosaic system and method May 20, 2008
A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a
7366238 Noise filter for video processing April 29, 2008
A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blo
7359006 Audio module supporting audio signature April 15, 2008
A system and method embed an audio signature in a video frame. An audio signature is generated from one bit a buffer input data. Two registers store an audio signature and reference count. According to an embodiment, the audio signature is generated left/right (L/R) interleaved with the
7333678 Edge adaptive demosaic system and method February 19, 2008
A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a
7310785 Video processing architecture definition by function graph methodology December 18, 2007
A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique
7259796 System and method for rapidly scaling and filtering video data August 21, 2007
This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined
7219173 System for video processing control and scheduling wherein commands are unaffected by signal int May 15, 2007
A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to th
7184101 Address generation for video processing February 27, 2007
A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a m
7142251 Video input processor in multi-format video compression system November 28, 2006
A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The
7136414 System and method for efficiently performing an inverse telecine procedure November 14, 2006
A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator

 
 
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