| Patent Number |
Title Of Patent |
Date Issued |
| 7563723 |
Critical dimension control for integrated circuits |
July 21, 2009 |
| Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the |
| 7563679 |
Reduction of field edge thinning in peripheral devices |
July 21, 2009 |
| A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that c |
| 7563666 |
Semiconductor structures including vertical diode structures and methods of making the same |
July 21, 2009 |
| Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be fo |
| 7563631 |
Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduc |
July 21, 2009 |
| A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed a |
| 7563157 |
Apparatus for conditioning chemical-mechanical polishing pads |
July 21, 2009 |
| An apparatus for conditioning a polishing pad, or conditioner, includes a supporting substrate and abrasive elements. The abrasive elements of the conditioner are used to condition a polishing pad to be used in abrasive, or at least partially mechanical, semiconductor substrate treatment |
| 7562268 |
Method and apparatus for testing a memory device with compressed data using a single output |
July 14, 2009 |
| A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test |
| 7562178 |
Memory hub and method for memory sequencing |
July 14, 2009 |
| A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics--for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory |
| 7561938 |
Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergon |
July 14, 2009 |
| An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a f |
| 7561477 |
Data strobe synchronization circuit and method for double data rate, multi-bit writes |
July 14, 2009 |
| A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data stro |
| 7561472 |
NAND architecture memory with voltage sensing |
July 14, 2009 |
| A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process |
| 7561469 |
Programming method to reduce word line to word line breakdown for NAND flash |
July 14, 2009 |
| A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell be |
| 7561466 |
Non-volatile memory copy back |
July 14, 2009 |
| Data move operations in a memory device are included that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory contr |
| 7560959 |
Absolute value peak differential voltage detector circuit and method |
July 14, 2009 |
| A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output |
| 7560956 |
Method and apparatus for selecting an operating mode based on a determination of the availabilit |
July 14, 2009 |
| A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output d |
| 7560816 |
Small grain size, conformal aluminum interconnects and method for their formation |
July 14, 2009 |
| A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientat |
| 7560815 |
Device structures including ruthenium silicide diffusion barrier layers |
July 14, 2009 |
| A device structure including a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSi.sub.x, where x is in the range of about 0.01 to about 10. Capacitor electrodes, interconnects or |
| 7560799 |
Spacer patterned, high dielectric constant capacitor |
July 14, 2009 |
| A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A central region of the barrier layer may be recessed relative to at least a portion of an outer periphery of the barrier layer |
| 7560793 |
Atomic layer deposition and conversion |
July 14, 2009 |
| A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the subsequent converting step includes oxidizing a metal atomic layer to form a metal oxide layer. The atomic layer deposition and |
| 7560769 |
Non-volatile memory cell device and methods |
July 14, 2009 |
| A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielect |
| 7560723 |
Enhanced memory density resistance variable memory cells, arrays, devices and systems including |
July 14, 2009 |
| A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one la |
| 7560395 |
Atomic layer deposited hafnium tantalum oxide dielectrics |
July 14, 2009 |
| A dielectric layer containing hafnium tantalum film arranged as a structure of one or more monolayers and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. In an embodiment, a hafnium tantalum oxide film may be form |
| 7560393 |
Systems and methods of forming refractory metal nitride layers using disilazanes |
July 14, 2009 |
| A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an opti |
| 7560392 |
Electrical components for microelectronic devices and methods of forming the same |
July 14, 2009 |
| Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by di |
| 7560390 |
Multiple spacer steps for pitch multiplication |
July 14, 2009 |
| Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, a |
| 7560371 |
Methods for selectively filling apertures in a substrate to form conductive vias with a liquid u |
July 14, 2009 |
| Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing the liquid material into the aperture with a vacuum. The wave may be formed by flowing the liquid material out from an outlet |
| 7560336 |
DRAM layout with vertical FETs and method of formation |
July 14, 2009 |
| DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are |
| 7560335 |
Memory device transistors |
July 14, 2009 |
| Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation |
| 7560305 |
Apparatus and method for high density multi-chip structures |
July 14, 2009 |
| Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. |
| 7560017 |
Methods and apparatus for electrically detecting characteristics of a microelectronic substrate |
July 14, 2009 |
| Methods and apparatuses for detecting characteristics of a microelectronic substrate. A method in accordance with an embodiment of the invention includes positioning the microelectronic substrate proximate to and spaced apart from the first and second spaced apart electrodes, contact |
| 7558142 |
Method and system for controlling refresh to avoid memory cell data losses |
July 7, 2009 |
| A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter |
| 7558133 |
System and method for capturing data signals using a data strobe signal |
July 7, 2009 |
| A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to |
| 7558131 |
NAND system with a data write frequency greater than a command-and-address-load frequency |
July 7, 2009 |
| The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second frequency that is greater than the first frequency. |
| 7558130 |
Adjustable drive strength apparatus, systems, and methods |
July 7, 2009 |
| Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die device and that provides the state of all of the dice at a common output. Such a multi-die device can comprise two or more dic |
| 7558125 |
Input buffer and method with AC positive feedback, and a memory device and computer system using |
July 7, 2009 |
| An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state r |
| 7558102 |
Device and method having a memory array storing each bit in multiple memory cells |
July 7, 2009 |
| A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store "1" and "0" bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the |
| 7557631 |
Voltage and temperature compensation delay system and method |
July 7, 2009 |
| A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that r |
| 7557628 |
Method and apparatus for digital phase generation at high frequencies |
July 7, 2009 |
| An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method fur |
| 7557620 |
System and method for controlling input buffer biasing current |
July 7, 2009 |
| A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a plurality of discrete biasing control signals. At least one input buffer is configured to adjust the biasing current in respons |
| 7557603 |
Method and apparatus for output driver calibration, and memory devices and system embodying same |
July 7, 2009 |
| A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel d |
| 7557601 |
Memory module and method having improved signal routing topology |
July 7, 2009 |
| A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another |
| 7557454 |
Assemblies with bond pads of two or more semiconductor devices electrically connected to the sam |
July 7, 2009 |
| A semiconductor device includes two or more semiconductor devices with bond pads that are electrically connected to the same, single surface of a plurality of leads. The two or more devices may include substantially centrally located bond pads or substantially identically arranged bond |
| 7557452 |
Reinforced, self-aligning conductive structures for semiconductor device components and methods |
July 7, 2009 |
| A conductive structure configured to connect a contact pad of a semiconductor device with a corresponding contact pad of a substrate. The conductive structure includes two interconnectable members, one securable to each of the corresponding contact pads. Each member includes a dielec |
| 7557443 |
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microele |
July 7, 2009 |
| Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the |
| 7557420 |
Low temperature process for polysilazane oxidation/densification |
July 7, 2009 |
| Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low |
| 7557345 |
Integrated circuit chips, apparatuses for obtaining backscatter data from samples, methods of ba |
July 7, 2009 |
| Some embodiments include methods for fabricating an alpha particle emitter and detector associated with an integrated circuit chip. Some embodiments include an integrated circuit chip comprising an alpha particle emitter and detector supported by a semiconductor substrate. Some embodimen |
| 7557048 |
Methods of forming semiconductor constructions |
July 7, 2009 |
| The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor |
| 7557047 |
Method of forming a layer of material using an atomic layer deposition process |
July 7, 2009 |
| Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse |
| 7557032 |
Silicided recessed silicon |
July 7, 2009 |
| Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals d |
| 7557024 |
Single poly CMOS imager |
July 7, 2009 |
| More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and |
| 7557015 |
Methods of forming pluralities of capacitors |
July 7, 2009 |
| The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lat |
