| Patent Number |
Title Of Patent |
Date Issued |
| 7567848 |
Speaker apparatus and a computer system incorporating same |
July 28, 2009 |
| An internal subwoofer apparatus is provided for mounting within a computer system. The computer system is a multi-media computer system that processes visual and audio recording and playback. The central processing unit box typically includes the motherboard on which is mounted the main |
| 7567477 |
Bias sensing in sense amplifiers through a voltage-coupling/decoupling device |
July 28, 2009 |
| Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplif |
| 7567472 |
Memory block testing |
July 28, 2009 |
| A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is le |
| 7567465 |
Power saving sensing scheme for solid state memory |
July 28, 2009 |
| Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining t |
| 7567462 |
Method and system for selectively limiting peak power consumption during programming or erase of |
July 28, 2009 |
| A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined |
| 7567461 |
Method and system for minimizing number of programming pulses used to program rows of non-volati |
July 28, 2009 |
| A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality o |
| 7567455 |
Method and system for programming non-volatile memory cells based on programming of proximate me |
July 28, 2009 |
| A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are |
| 7567091 |
Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor |
July 28, 2009 |
| A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circu |
| 7566907 |
Thin film transistors and semiconductor constructions |
July 28, 2009 |
| A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycryst |
| 7566620 |
DRAM including a vertical surround gate transistor |
July 28, 2009 |
| DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line con |
| 7566601 |
Method of making a one transistor SOI non-volatile random access memory cell |
July 28, 2009 |
| One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the bu |
| 7566600 |
SOI device with reduced drain induced barrier lowering |
July 28, 2009 |
| A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the |
| 7566391 |
Methods and systems for removing materials from microfeature workpieces with organic and/or non- |
July 28, 2009 |
| Methods and systems for removing materials from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes providing a microfeature workpiece having a substrate material and a conductive material that includes a refractory metal (e.g., |
| 7566257 |
Method and system for transferring data to an electronic toy or other electronic device |
July 28, 2009 |
| A method for transferring data from a display device to an electronic device includes displaying a visual pattern on the display device. The visual pattern represents the data being transferred. In the electronic device, the visual pattern is received and processed to obtain the data |
| 7565587 |
Background block erase check for flash memories |
July 21, 2009 |
| Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory |
| 7565039 |
Resistive heater for thermo optic device |
July 21, 2009 |
| Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing methods. The resistive heater is comprised of a heater region and a conductive path region formed together in a first mask count |
| 7564733 |
Memory device and method having programmable address configurations |
July 21, 2009 |
| A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are si |
| 7564731 |
Software refreshed memory device and method |
July 21, 2009 |
| A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared |
| 7564722 |
Memory system and method having volatile and non-volatile memory devices at same hierarchical le |
July 21, 2009 |
| A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access mem |
| 7564721 |
Method and apparatus for improving storage performance using a background erase |
July 21, 2009 |
| Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of ass |
| 7564397 |
High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-t |
July 21, 2009 |
| An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the firs |
| 7564279 |
Power on reset circuitry in electronic systems |
July 21, 2009 |
| One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment includes providing a voltage to a POR circuit of the system, detecting when the voltage reaches a number of different trip level |
| 7564088 |
High-density single transistor vertical memory gain cell |
July 21, 2009 |
| A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pill |
| 7564087 |
Merged MOS-bipolar capacitor memory cell |
July 21, 2009 |
| A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor havin |
| 7564082 |
Gettering using voids formed by surface transformation |
July 21, 2009 |
| One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transfo |
| 7563730 |
Hafnium lanthanide oxynitride films |
July 21, 2009 |
| Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be dispose |
| 7563723 |
Critical dimension control for integrated circuits |
July 21, 2009 |
| Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma is used to etch an amorphous carbon hard mask layer. The features of a pattern can be shrunk using a plasma etch to reduce the |
| 7563679 |
Reduction of field edge thinning in peripheral devices |
July 21, 2009 |
| A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that c |
| 7563666 |
Semiconductor structures including vertical diode structures and methods of making the same |
July 21, 2009 |
| Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be fo |
| 7563631 |
Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduc |
July 21, 2009 |
| A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the same are disclosed. Embodiments of the invention provide a pixel cell comprising a substrate. A gate of a transistor is formed a |
| 7563157 |
Apparatus for conditioning chemical-mechanical polishing pads |
July 21, 2009 |
| An apparatus for conditioning a polishing pad, or conditioner, includes a supporting substrate and abrasive elements. The abrasive elements of the conditioner are used to condition a polishing pad to be used in abrasive, or at least partially mechanical, semiconductor substrate treatment |
| 7562268 |
Method and apparatus for testing a memory device with compressed data using a single output |
July 14, 2009 |
| A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data is written to cells in a memory device, the cells are read to generate read data, the read data is compressed to generate test |
| 7562178 |
Memory hub and method for memory sequencing |
July 14, 2009 |
| A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics--for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory |
| 7561938 |
Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergon |
July 14, 2009 |
| An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a f |
| 7561477 |
Data strobe synchronization circuit and method for double data rate, multi-bit writes |
July 14, 2009 |
| A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data stro |
| 7561472 |
NAND architecture memory with voltage sensing |
July 14, 2009 |
| A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process |
| 7561469 |
Programming method to reduce word line to word line breakdown for NAND flash |
July 14, 2009 |
| A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell be |
| 7561466 |
Non-volatile memory copy back |
July 14, 2009 |
| Data move operations in a memory device are included that enable identification of data errors. During a write operation, identified errors are flagged and used to provide an error status during the data move operation. Results of the error detection can be accessed by a memory contr |
| 7560959 |
Absolute value peak differential voltage detector circuit and method |
July 14, 2009 |
| A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output |
| 7560956 |
Method and apparatus for selecting an operating mode based on a determination of the availabilit |
July 14, 2009 |
| A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output d |
| 7560816 |
Small grain size, conformal aluminum interconnects and method for their formation |
July 14, 2009 |
| A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientat |
| 7560815 |
Device structures including ruthenium silicide diffusion barrier layers |
July 14, 2009 |
| A device structure including a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSi.sub.x, where x is in the range of about 0.01 to about 10. Capacitor electrodes, interconnects or |
| 7560799 |
Spacer patterned, high dielectric constant capacitor |
July 14, 2009 |
| A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A central region of the barrier layer may be recessed relative to at least a portion of an outer periphery of the barrier layer |
| 7560793 |
Atomic layer deposition and conversion |
July 14, 2009 |
| A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the subsequent converting step includes oxidizing a metal atomic layer to form a metal oxide layer. The atomic layer deposition and |
| 7560769 |
Non-volatile memory cell device and methods |
July 14, 2009 |
| A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielect |
| 7560723 |
Enhanced memory density resistance variable memory cells, arrays, devices and systems including |
July 14, 2009 |
| A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable material in contact with the first electrode. A first, second electrode is in contact with a first portion of the at least one la |
| 7560395 |
Atomic layer deposited hafnium tantalum oxide dielectrics |
July 14, 2009 |
| A dielectric layer containing hafnium tantalum film arranged as a structure of one or more monolayers and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. In an embodiment, a hafnium tantalum oxide film may be form |
| 7560393 |
Systems and methods of forming refractory metal nitride layers using disilazanes |
July 14, 2009 |
| A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier layer, on a substrate by using a vapor deposition process with a refractory metal precursor compound, a disilazane, and an opti |
| 7560392 |
Electrical components for microelectronic devices and methods of forming the same |
July 14, 2009 |
| Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by di |
| 7560390 |
Multiple spacer steps for pitch multiplication |
July 14, 2009 |
| Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, a |
