| Patent Number |
Title Of Patent |
Date Issued |
| 7576398 |
Method of composite gate formation |
August 18, 2009 |
| Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier |
| 7576380 |
Methods for enhancing capacitors having roughened features to increase charge-storage capacity |
August 18, 2009 |
| Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the |
| 7576378 |
Systems and methods for forming metal oxides using metal diketonates and/or ketoimines |
August 18, 2009 |
| A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include diketonate ligands and/or ketoimine ligands. |
| 7576012 |
Atomic layer deposition methods |
August 18, 2009 |
| A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma co |
| 7575999 |
Method for creating conductive elements for semiconductor device structures using laser ablation |
August 18, 2009 |
| A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielect |
| 7575978 |
Method for making conductive nanoparticle charge storage element |
August 18, 2009 |
| Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as |
| 7575953 |
Stacked die with a recess in a die BGA package |
August 18, 2009 |
| Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. |
| 7574634 |
Real time testing using on die termination (ODT) circuit |
August 11, 2009 |
| A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, may be transferred |
| 7574466 |
Method for finding global extrema of a set of shorts distributed across an array of parallel pro |
August 11, 2009 |
| A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each processing element a first dimensional extrema for a first dimension, wherein the first dimensional extrema is related to the local extrem |
| 7574309 |
Internal bias measure with onboard ADC for electronic devices |
August 11, 2009 |
| An apparatus and method for on-chip bias measurement of an analog signals on an integrated circuit with a switchable analog-to-digital converter capable of performing testing and other types of processing. Analog signal test locations are selected for testing by a test input selector |
| 7573752 |
NAND flash memory cell programming |
August 11, 2009 |
| A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. |
| 7573738 |
Mode selection in a flash memory device |
August 11, 2009 |
| A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode |
| 7573733 |
Self-identifying stacked die semiconductor components |
August 11, 2009 |
| A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automat |
| 7573288 |
Dynamically adjusting operation of a circuit within a semiconductor device |
August 11, 2009 |
| Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled to each other in |
| 7573276 |
Probe card layout |
August 11, 2009 |
| Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater than 99% efficiency during testing of a substrate having a plurality of die thereon, and methods of use. |
| 7573136 |
Semiconductor device assemblies and packages including multiple semiconductor device components |
August 11, 2009 |
| A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g., semiconductor devices) may be assembled with the interposer. For example, at least one co |
| 7573125 |
Methods for reducing stress in microelectronic devices and microelectronic devices formed using |
August 11, 2009 |
| Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first support member and the |
| 7573121 |
Method for enhancing electrode surface area in DRAM cell capacitors |
August 11, 2009 |
| Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a |
| 7573116 |
Etch aided by electrically shorting upper and lower sidewall portions during the formation of a |
August 11, 2009 |
| A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate the |
| 7573113 |
Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method |
August 11, 2009 |
| A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5. |
| 7573108 |
Non-planar transistor and techniques for fabricating the same |
August 11, 2009 |
| A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate may be switchably coupled to a first voltage that is configured to turn on the transistor, and the passive gate may be fixedly |
| 7573088 |
DRAM array and electronic system |
August 11, 2009 |
| The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is |
| 7573087 |
Interconnect line selectively isolated from an underlying contact plug |
August 11, 2009 |
| A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as |
| 7573006 |
Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing |
August 11, 2009 |
| Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplet |
| 7572731 |
Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and metho |
August 11, 2009 |
| The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In some embodiments, the metal-containing compounds are homoleptic complexes that include unsymmetrical .beta.-diketiminate ligands. I |
| 7572725 |
Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed |
August 11, 2009 |
| Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the m |
| 7572710 |
Methods of forming conductive contacts to source/drain regions and methods of forming local inte |
August 11, 2009 |
| The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor inc |
| 7572695 |
Hafnium titanium oxide films |
August 11, 2009 |
| Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety |
| 7572678 |
Methods of making and using a floating lead finger on a lead frame |
August 11, 2009 |
| A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating no-connect (NC) lead fingers with inner portions of the floating NC lead fingers electrically isolated from |
| 7572670 |
Methods of forming semiconductor packages |
August 11, 2009 |
| The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and having portions extending over the openings, a semiconductor die over the circuit traces, and a matrix contacting the circ |
| 7572572 |
Methods for forming arrays of small, closely spaced features |
August 11, 2009 |
| Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography s |
| 7572385 |
Method of forming micro-lenses |
August 11, 2009 |
| A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is comprised of a second material. An opening is formed in the first layer and an etchant is provided in the opening to etch both t |
| 7570538 |
Method for writing to multiple banks of a memory device |
August 4, 2009 |
| In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one |
| 7570521 |
Low power flash memory devices |
August 4, 2009 |
| A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrie |
| 7570504 |
Device and method to reduce wordline RC time constant in semiconductor memory devices |
August 4, 2009 |
| A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using prior art techniqu |
| 7570293 |
Image sensor with on-chip semi-column-parallel pipeline ADCS |
August 4, 2009 |
| An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined mann |
| 7570069 |
Resilient contact probes |
August 4, 2009 |
| Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different embodiments for the resilient contact probes is also disclosed. The carriers of the present invention may be secured to an interface |
| 7569934 |
Copper interconnect |
August 4, 2009 |
| An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on |
| 7569915 |
Shielding arrangement to protect a circuit from stray magnetic fields |
August 4, 2009 |
| A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Al |
| 7569876 |
DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DR |
August 4, 2009 |
| The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, |
| 7569485 |
Method for an integrated circuit contact |
August 4, 2009 |
| A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The proce |
| 7569484 |
Plasma and electron beam etching device and method |
August 4, 2009 |
| Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemic |
| 7569473 |
Methods of forming semiconductor assemblies |
August 4, 2009 |
| Apparatus and methods are disclosed relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in el |
| 7569468 |
Method for forming a floating gate memory with polysilicon local interconnects |
August 4, 2009 |
| Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing |
| 7569453 |
Contact structure |
August 4, 2009 |
| This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircl |
| 7569418 |
Methods for securing packaged semiconductor devices to carrier substrates |
August 4, 2009 |
| A method for securing a semiconductor device to a carrier substrate includes inserting a semiconductor device with a plurality of stub contacts extending from a bottom edge thereof into a receptacle of an alignment device associated with the carrier substrate. Upon attachment of the |
| 7569414 |
CMOS imager with integrated non-volatile memory |
August 4, 2009 |
| A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking lig |
| 7569314 |
Method for quartz bump defect repair with less substrate damage |
August 4, 2009 |
| A method for minimizing damage to a substrate while repairing a defect in a phase shifting mask for an integrated circuit comprising locating a bump defect in a phase shifting mask, depositing a first layer of protective coating to an upper surface of the bump defect, depositing a se |
| 7569311 |
Method of forming a pattern using a polarized reticle in conjunction with polarized light |
August 4, 2009 |
| Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed having a reticle containing at least one first patterned region at least partially surrounded by at least one second patterned r |
| 7568970 |
Chemical mechanical polishing pads |
August 4, 2009 |
| The present invention provides a deformable pad useful for chemical mechanical polishing ("CMP"), a CMP apparatus incorporating the deformable pad of the present invention, and methods for using the deformable pad and CMP apparatus of the present invention. The deformable pad of the |
