| Patent Number |
Title Of Patent |
Date Issued |
| 7586777 |
Resistance variable memory with temperature tolerant materials |
September 8, 2009 |
| A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a metal-chalcogenide layer and methods of forming such a memory device. |
| 7586329 |
Capacitively-coupled level restore circuits for low voltage swing logic circuits |
September 8, 2009 |
| Some embodiments of the disclosure include a circuit having differential sides and a capacitive network coupled to differential sides. The circuit further includes a reset network for resetting the first differential side to a first voltage and for resetting the second differential side |
| 7586319 |
Methods of retaining semiconductor component configurations within sockets |
September 8, 2009 |
| The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that compression of the sockets opens a clamping mechanism. A chip can be placed within a socket |
| 7586144 |
Memory device with high dielectric constant gate dielectrics and metal floating gates |
September 8, 2009 |
| A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are |
| 7585782 |
Methods of forming semiconductor constructions, and methods of selectively removing metal-contai |
September 8, 2009 |
| The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing materials and tungsten-containing materials) relative to oxide (such as silicon dioxide) and/or copper. The selective removal c |
| 7585753 |
Controlling diffusion in doped semiconductor regions |
September 8, 2009 |
| A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a |
| 7585741 |
Methods of forming capacitors |
September 8, 2009 |
| The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lat |
| 7585728 |
Methods of programming memory cells using manipulation of oxygen vacancies |
September 8, 2009 |
| One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be |
| 7585725 |
Use of dilute steam ambient for improvement of flash devices |
September 8, 2009 |
| The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing th |
| 7585707 |
Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transisto |
September 8, 2009 |
| A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage. |
| 7585425 |
Apparatus and method for reducing removal forces for CMP pads |
September 8, 2009 |
| An improvement in a polishing apparatus for planarizing substrates comprises a tenacious coating of a low-adhesion material to the platen surface. An expendable polishing pad is adhesively attached to the low-adhesion material, and may be removed for periodic replacement at much redu |
| 7585371 |
Substrate susceptors for receiving semiconductor substrates to be deposited upon |
September 8, 2009 |
| In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includ |
| 7584942 |
Ampoules for producing a reaction gas and systems for depositing materials onto microfeature wor |
September 8, 2009 |
| Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in reaction chambers are disclosed herein. In one embodiment, an ampoule includes a vessel having an interior volume configured to receive a precursor with a headspace above the precur |
| 7584343 |
Data reordering processor and method for use in an active memory device |
September 1, 2009 |
| An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also genera |
| 7583551 |
Power management control and controlling memory refresh operations |
September 1, 2009 |
| A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and |
| 7583358 |
Systems and methods for retrieving residual liquid during immersion lens photolithography |
September 1, 2009 |
| Systems and methods for retrieving residual liquid during immersion lens photolithography are disclosed. A method in accordance with one embodiment includes directing radiation along a radiation path, through a lens and through a liquid volume in contact with the lens, to a microfeat |
| 7583115 |
Delay line off-state control with power reduction |
September 1, 2009 |
| A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least o |
| 7583070 |
Zero power start-up circuit for self-bias circuit |
September 1, 2009 |
| An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its operation in its desired stable state. Once the self-bias circuit converges to its desired state of operation a start-up vo |
| 7582570 |
Compositions for removal of processing byproducts and method for using same |
September 1, 2009 |
| A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine co |
| 7582562 |
Atomic layer deposition methods |
September 1, 2009 |
| An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises |
| 7582561 |
Method of selectively depositing materials on a substrate using a supercritical fluid |
September 1, 2009 |
| A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a polymer film to at least a portion of a surface of the substrate; and exposing the semiconductor substrate to a supercritical |
| 7582549 |
Atomic layer deposited barium strontium titanium oxide films |
September 1, 2009 |
| Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric lay |
| 7582180 |
Systems and methods for processing microfeature workpieces |
September 1, 2009 |
| Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece processing site configured to receive a microfeature workpiece and a main inlet through which a processing fluid can flow into |
| 7582161 |
Atomic layer deposited titanium-doped indium oxide films |
September 1, 2009 |
| An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The f |
| 7581511 |
Apparatus and methods for manufacturing microfeatures on workpieces using plasma vapor processes |
September 1, 2009 |
| A reactor comprising an energy source, a plasma unit positioned relative to the energy source, and a processing vessel connected to the plasma unit. The energy source has a generator that produces a plasma energy and a transmitter to transmit the plasma energy. The plasma unit has a firs |
| 7581080 |
Method for manipulating data in a group of processing elements according to locally maintained c |
August 25, 2009 |
| The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in any desired manner. |
| 7581055 |
Multiple processor system and method including multiple memory hub modules |
August 25, 2009 |
| A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory |
| 7580887 |
Method and apparatus for facilitating purchase transactions across a network |
August 25, 2009 |
| A local computer system that provides and records information to facilitate a purchase transaction across a network operates by first receiving a request for billing information relating to a purchase transaction from a remote computer system. The local system then retrieves the bill |
| 7580287 |
Program and read trim setting |
August 25, 2009 |
| A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability. |
| 7580286 |
Selective threshold voltage verification and compaction |
August 25, 2009 |
| Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on |
| 7580283 |
System and memory for sequential multi-plane page memory operations |
August 25, 2009 |
| A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the |
| 7580279 |
Flash memory cells with reduced distances between cell elements |
August 25, 2009 |
| An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of the etched areas of the ARC slope downward at an angle determined by the thickness of the ARC. The etching process could inc |
| 7579862 |
MOS linear region impedance curvature correction |
August 25, 2009 |
| A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region curvature correction |
| 7579684 |
Methods for packing microfeature devices and microfeature devices formed by such methods |
August 25, 2009 |
| Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of |
| 7579681 |
Super high density module with integrated wafer level packages |
August 25, 2009 |
| A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In o |
| 7579615 |
Access transistor for memory device |
August 25, 2009 |
| An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one |
| 7579278 |
Topography directed patterning |
August 25, 2009 |
| A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by |
| 7579267 |
Methods and systems for fabricating semiconductor components with through wire interconnects (TW |
August 25, 2009 |
| A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded |
| 7579242 |
High performance multi-level non-volatile memory device |
August 25, 2009 |
| Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and ch |
| 7579240 |
Method of making vertical transistor with horizontal gate layers |
August 25, 2009 |
| Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effe |
| 7579235 |
Container capacitor structure and method of formation thereof |
August 25, 2009 |
| Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess between proximal pairs of container |
| 7578056 |
Method of coating contacts on a surface of a flip chip |
August 25, 2009 |
| A method for encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer to the surface of the flip chip except for the distal end of the conductive projections on the flip chip electrically conductive pads. The coated |
| 7577830 |
Peripheral device with hardware linked list |
August 18, 2009 |
| A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a querying device. The |
| 7577790 |
Caching of dynamic arrays |
August 18, 2009 |
| Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing acces |
| 7577212 |
Method and system for generating reference voltages for signal receivers |
August 18, 2009 |
| A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled |
| 7577044 |
Resistive memory element sensing using averaging |
August 18, 2009 |
| A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected |
| 7577036 |
Non-volatile multilevel memory cells with data read of reference cells |
August 18, 2009 |
| Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line |
| 7577027 |
Multi-state memory cell with asymmetric charge trapping |
August 18, 2009 |
| A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the ox |
| 7576441 |
Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semicond |
August 18, 2009 |
| A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon hard mask layers. |
| 7576400 |
Circuitry and gate stacks |
August 18, 2009 |
| The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which enc |
