| Patent Number |
Title Of Patent |
Date Issued |
| 7604527 |
Methods and systems for planarizing workpieces, e.g., microelectronic workpieces |
October 20, 2009 |
| Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a planarizing condition. This process indicator may, for example, change color in response to reaching a particular temperature or in |
| 7603772 |
Methods of fabricating substrates including one or more conductive vias |
October 20, 2009 |
| Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a |
| 7603534 |
Synchronous flash memory with status burst output |
October 13, 2009 |
| A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such a |
| 7603493 |
Dynamically setting burst length of memory device by applying signal to at least one external pi |
October 13, 2009 |
| One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. |
| 7602876 |
Method and apparatus for generating a phase dependent control signal |
October 13, 2009 |
| A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having |
| 7602630 |
Configurable inputs and outputs for memory stacking system and method |
October 13, 2009 |
| Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular sign |
| 7602618 |
Methods and apparatuses for transferring heat from stacked microfeature devices |
October 13, 2009 |
| Apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The fi |
| 7602049 |
Capacitive techniques to reduce noise in high speed interconnections |
October 13, 2009 |
| Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. Embodiments of an electronic device having a transmission line circuit include a first layer of electrically conductive materi |
| 7602039 |
Programmable capacitor associated with an input/output pad |
October 13, 2009 |
| The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconduc |
| 7602030 |
Hafnium tantalum oxide dielectrics |
October 13, 2009 |
| A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with |
| 7602009 |
Erasable non-volatile memory device using hole trapping in high-K dielectrics |
October 13, 2009 |
| A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control gate and a channel region of a transistor to trap positively charged holes. The multilayer charge trapping dielectric compri |
| 7602001 |
Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorles |
October 13, 2009 |
| This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first |
| 7601649 |
Zirconium-doped tantalum oxide films |
October 13, 2009 |
| A dielectric film containing zirconium-doped tantalum oxide arranged as a structure of one or more monolayers and a method of fabricating such a dielectric film produce a reliable dielectric layer for use in a variety of electronic devices. In an embodiment, a zirconium-doped tantalum ox |
| 7601598 |
Reverse metal process for creating a metal silicide transistor gate structure |
October 13, 2009 |
| The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate ox |
| 7601595 |
Surround gate access transistors with grown ultra-thin bodies |
October 13, 2009 |
| A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body |
| 7601593 |
Flash memory with metal-insulator-metal tunneling program and erase |
October 13, 2009 |
| The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the control |
| 7601591 |
Method of manufacturing sidewall spacers on a memory device, and device comprising same |
October 13, 2009 |
| The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array |
| 7601586 |
Methods of forming buried bit line DRAM circuitry |
October 13, 2009 |
| A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is |
| 7601562 |
Microelectronic component assemblies having lead frames adapted to reduce package bow |
October 13, 2009 |
| The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, the invention provides a microelectronic component assembly that includes spaced-apart first and se |
| 7601547 |
Magnetic annealing sequences for patterned MRAM synthetic antiferromagnetic pinned layers |
October 13, 2009 |
| A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first t |
| 7601283 |
Methods and apparatuses for shaping a printed circuit board |
October 13, 2009 |
| Methods and apparatuses for shaping a corner of a printed circuit board are disclosed. An apparatus in accordance with one embodiment includes a carrier configured to releasably contact a printed circuit board, a curved contact surface positioned to roll against a corner of the printed |
| 7600314 |
Methods for installing a plurality of circuit devices |
October 13, 2009 |
| A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the |
| 7598181 |
Process for enhancing solubility and reaction rates in supercritical fluids |
October 6, 2009 |
| Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of |
| 7598167 |
Method of forming vias in semiconductor substrates without damaging active regions thereof and r |
October 6, 2009 |
| Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate unde |
| 7598165 |
Methods for forming a multiplexer of a memory device |
October 6, 2009 |
| A method of forming a portion of a multiplexer of a memory device includes forming a plurality of conductive plugs on a semiconductor substrate and forming first and second bit lines overlying the conductive plugs so that a pair of successively adjacent first and second bit lines is in c |
| 7598134 |
Memory device forming methods |
October 6, 2009 |
| A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, |
| 7598132 |
Active photosensitive structure with buried depletion layer |
October 6, 2009 |
| An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integratio |
| 7598021 |
High resolution printing technique |
October 6, 2009 |
| A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is printed using an array of probes, each probe having: 1) a photocatalytic nanodot at its tip; and 2) an individually controlled l |
| 7596729 |
Memory device testing system and method using compressed fail data |
September 29, 2009 |
| A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data |
| 7596678 |
Method of shifting data along diagonals in a group of processing elements to transpose the data |
September 29, 2009 |
| A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal have received the data held by every other processing element in that diagonal. Shifti |
| 7596675 |
Memory hub architecture having programmable lane widths |
September 29, 2009 |
| A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bu |
| 7596641 |
System and method for transmitting data packets in a computer system having a memory hub archite |
September 29, 2009 |
| A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes |
| 7596052 |
Method and apparatus for reducing oscillation in synchronous circuits |
September 29, 2009 |
| Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter |
| 7596039 |
Input-output line sense amplifier having adjustable output drive capability |
September 29, 2009 |
| An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the |
| 7596035 |
Memory device bit line sensing system and method that compensates for bit line resistance variat |
September 29, 2009 |
| Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and |
| 7595844 |
Method for assisting video compression in a computer system |
September 29, 2009 |
| One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees |
| 7595521 |
Terraced film stack |
September 29, 2009 |
| A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addresse |
| 7594322 |
Methods of fabricating substrates including at least one conductive via |
September 29, 2009 |
| A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. A |
| 7594257 |
Data security for digital data storage |
September 22, 2009 |
| A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be network resident. The data encryption may utilize a key which is derived at least in part from an identification code stored |
| 7594088 |
System and method for an asynchronous data buffer having buffer write and read pointers |
September 22, 2009 |
| A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset repre |
| 7593287 |
READ command triggered synchronization circuitry |
September 22, 2009 |
| A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization circuit achieves a signal lock with the reference clock signal in less time than the column address strobe latency. Precise m |
| 7593286 |
Write latency tracking using a delay lock loop in a synchronous DRAM |
September 22, 2009 |
| A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in |
| 7593272 |
Detection of row-to-row shorts and other row decode defects in memory devices |
September 22, 2009 |
| A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path |
| 7593254 |
Variable resistance memory device with an interfacial adhesion heating layer, systems using the |
September 22, 2009 |
| A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a first surface coupled to said first electrode; a resistance changing material, e.g. a phase change material, having a first sur |
| 7592691 |
High density stacked die assemblies, structures incorporated therein and methods of fabricating |
September 22, 2009 |
| A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddl |
| 7592251 |
Hafnium tantalum titanium oxide films |
September 22, 2009 |
| Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in |
| 7592246 |
Method and semiconductor device having copper interconnect for bonding |
September 22, 2009 |
| An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on |
| 7592242 |
Apparatus and method for controlling diffusion |
September 22, 2009 |
| A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic ra |
| 7592218 |
Methods of forming vertical transistors |
September 22, 2009 |
| A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over |
| 7592212 |
Methods for determining a dose of an impurity implanted in a semiconductor substrate |
September 22, 2009 |
| Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity |
