| Patent Number |
Title Of Patent |
Date Issued |
| 7612436 |
Packaged microelectronic devices with a lead frame |
November 3, 2009 |
| Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at least one die in a stacked configuration attached to the support member. The |
| 7612403 |
Low power non-volatile memory and gate stack |
November 3, 2009 |
| Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, wh |
| 7612393 |
Active photosensitive structure with buried depletion layer |
November 3, 2009 |
| An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integratio |
| 7611980 |
Single spacer process for multiplying pitch by a factor greater than two and related intermediat |
November 3, 2009 |
| Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n.gtoreq.2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels a |
| 7611971 |
Method of removing residual contaminants from an environment |
November 3, 2009 |
| A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product |
| 7611959 |
Zr-Sn-Ti-O films |
November 3, 2009 |
| A dielectric layer containing a Zr--Sn--Ti--O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO.sub.2. In an embodiment, forming the Zr--Sn--Ti--O film on a substrate inc |
| 7611944 |
Integrated circuit fabrication |
November 3, 2009 |
| A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a low |
| 7611809 |
Multi-layer, attenuated phase-shifting mask |
November 3, 2009 |
| The present invention provides an attenuated phase shift mask ("APSM") that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions |
| 7610525 |
Defective memory block identification in a memory device |
October 27, 2009 |
| During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal ope |
| 7610524 |
Memory with test mode output |
October 27, 2009 |
| Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus. |
| 7610503 |
Methods for generating a delayed clock signal |
October 27, 2009 |
| An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the sy |
| 7610502 |
Computer systems having apparatus for generating a delayed clock signal |
October 27, 2009 |
| An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the sy |
| 7610430 |
System and method for memory hub-based expansion bus |
October 27, 2009 |
| A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub |
| 7609583 |
Selective edge phase mixing |
October 27, 2009 |
| Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. |
| 7609565 |
External clock tracking pipelined latch scheme |
October 27, 2009 |
| A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second c |
| 7609563 |
Simultaneous read circuit for multiple memory cells |
October 27, 2009 |
| A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing state. |
| 7609560 |
Sensing of memory cells in a solid state memory device by fixed discharge of a bit line |
October 27, 2009 |
| In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by |
| 7609559 |
Word line drivers having a low pass filter circuit in non-volatile memory device |
October 27, 2009 |
| A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The |
| 7609557 |
Non-volatile memory cell read failure reduction |
October 27, 2009 |
| The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in |
| 7609554 |
High voltage switching circuit |
October 27, 2009 |
| A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and, an enhancement mode NMOS transistor. A control circuit generates first and second control signals. A first control signal controls the enhancement mode NMOS transistor |
| 7609549 |
Non-volatile multilevel memory cell programming |
October 27, 2009 |
| Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold |
| 7609302 |
Correction of non-uniform sensitivity in an image array |
October 27, 2009 |
| An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries which can be reconfigured depending upon the type of lens being used in a given application. Each pixel within each zone is |
| 7608927 |
Localized biasing for silicon on insulator structures |
October 27, 2009 |
| A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the |
| 7608904 |
Semiconductor device components with conductive vias and systems including the components |
October 27, 2009 |
| A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including |
| 7608876 |
Merged MOS-bipolar capacitor memory cell |
October 27, 2009 |
| A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor havin |
| 7608788 |
Plating buss and a method of use thereof |
October 27, 2009 |
| The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing sho |
| 7608495 |
Transistor forming methods |
October 27, 2009 |
| A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and forming a gate line extending through the line openings, over opposing sidewalls, and over a top of the fin. Source/drain regions |
| 7608196 |
Method of forming high aspect ratio apertures |
October 27, 2009 |
| A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF.sub.3 and CH.sub.2F.sub.2, delivered at flow rates on the ord |
| 7608195 |
High aspect ratio contacts |
October 27, 2009 |
| A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty (50) percent He to a plasma etch reactor, and exposing the insulating layer to a plasma of the first gaseous etchant. Use of t |
| 7607177 |
Secure compact flash |
October 20, 2009 |
| An embodiment of the present invention includes a nonvolatile memory card including a controller and nonvolatile memory coupled to the controller, the controller causing communication between the nonvolatile memory and a host, the nonvolatile memory including active memory for securing a |
| 7606448 |
Zinc oxide diodes for optical interconnections |
October 20, 2009 |
| The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has |
| 7606102 |
Memory address repair without enable fuses |
October 20, 2009 |
| A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separa |
| 7606101 |
Circuit and method for controlling a clock synchronizing circuit for low power refresh operation |
October 20, 2009 |
| A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is |
| 7606097 |
Array sense amplifiers, memory devices and systems including same, and methods of operation |
October 20, 2009 |
| A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output ("I/O") node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. T |
| 7606088 |
Sense amplifier circuit |
October 20, 2009 |
| The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide |
| 7606075 |
Read operation for NAND memory |
October 20, 2009 |
| Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not a |
| 7606055 |
Memory architecture and cell design employing two access transistors |
October 20, 2009 |
| An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. |
| 7605934 |
Method and system for facsimile delivery using dial-up modem pools |
October 20, 2009 |
| A method and system for communicating a facsimile (fax) message over a computer network. A user initiates the sending of the fax to a recipient fax transceiver located outside the user's local-toll area of a Public Switched Telephone Network (PSTN). A first fax transceiver transmits the |
| 7605852 |
Real-time exposure control for automatic light control |
October 20, 2009 |
| An imager and a method for real-time, non-destructive monitoring of light incident on imager pixels during their exposure to light. Real-time or present pixel signals, which are indicative of present illumination on the pixels, are compared to a reference signal during the exposure. |
| 7605650 |
Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy |
October 20, 2009 |
| A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples |
| 7605631 |
Delay line synchronizer apparatus and method |
October 20, 2009 |
| A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals |
| 7605620 |
System and method to improve the efficiency of synchronous mirror delays and delay locked loops |
October 20, 2009 |
| A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal |
| 7605611 |
Methods, devices, and systems for a high voltage tolerant buffer |
October 20, 2009 |
| Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondar |
| 7605417 |
Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially aro |
October 20, 2009 |
| The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers |
| 7605350 |
System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing |
October 20, 2009 |
| In general, the system provides for soft baking a semiconductor wafer so that photoresist layers on the wafer are free of surface voids or craters. In particular, the system provides for manufacturing a semiconductor wafer having no photoresist craters at the completion of a two-step |
| 7605034 |
Integrated circuit memory cells and methods of forming |
October 20, 2009 |
| An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The s |
| 7605033 |
Low resistance peripheral local interconnect contacts with selective wet strip of titanium |
October 20, 2009 |
| Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. In some embodiments, the method includes forming a metallized contact to an active area in |
| 7605030 |
Hafnium tantalum oxynitride high-k dielectric and metal gates |
October 20, 2009 |
| Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic |
| 7605028 |
Method of forming a memory device having a storage transistor |
October 20, 2009 |
| A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. |
| 7604729 |
Methods and apparatus for selectively removing conductive material from a microelectronic substr |
October 20, 2009 |
| Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the invention includes positioning the microelectronic substrate proximate to and spaced apart from an electrode pair that includes a f |
