| Patent Number |
Title Of Patent |
Date Issued |
| 7622798 |
Integrated circuit devices with stacked package interposers |
November 24, 2009 |
| An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a first bond pad of the die directly to a bond pad of the first interposer and a second conductive connection from a second bond |
| 7622772 |
Electronic apparatuses, silicon-on-insulator integrated circuits, and fabrication methods |
November 24, 2009 |
| An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to |
| 7622377 |
Microfeature workpiece substrates having through-substrate vias, and associated methods of forma |
November 24, 2009 |
| Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment for forming a support substrate for carrying microfeature dies includes exposing a support substrate to an electrolyte, with |
| 7622365 |
Wafer processing including dicing |
November 24, 2009 |
| Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on si |
| 7622355 |
Write once read only memory employing charge trapping in insulators |
November 24, 2009 |
| Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain region, a channel regio |
| 7622321 |
High dielectric constant spacer for imagers |
November 24, 2009 |
| An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency. |
| 7622049 |
Passivation for cleaning a material |
November 24, 2009 |
| A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before be |
| 7620859 |
Filtered register architecture to generate actuator signals |
November 17, 2009 |
| In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, |
| 7620789 |
Out of order DRAM sequencer |
November 17, 2009 |
| Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the re |
| 7620788 |
Memory device sequencer and method supporting multiple memory device clock speeds |
November 17, 2009 |
| A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the |
| 7620768 |
Multiple erase block tagging in a flash memory device |
November 17, 2009 |
| A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks |
| 7619933 |
Reducing effects of program disturb in a memory device |
November 17, 2009 |
| The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive V.sub.pass voltage. The selected word lines are biased with a programming voltage. In one embodi |
| 7619931 |
Program-verify method with different read and verify pass-through voltages |
November 17, 2009 |
| Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a ce |
| 7619670 |
Rolling shutter for prevention of blooming |
November 17, 2009 |
| A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling shutter progresses down the array, each row is hard reset multiple times before its integration period begins, thereby ens |
| 7619624 |
Methods and apparatus for rendering or preparing digital objects or portions thereof for subsequ |
November 17, 2009 |
| Methods and apparatus for rendering images of digital objects or for preparing digital objects for subsequent processing. The method includes sorting data representative of the positions of at least three vertices of at least one polygon of a digital object, then determining whether the |
| 7619458 |
Delay-lock loop and method adapting itself to operate over a wide frequency range |
November 17, 2009 |
| A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the |
| 7619453 |
Delay-locked loop (DLL) system for determining forward clock path delay |
November 17, 2009 |
| A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock |
| 7619449 |
Method and apparatus for synchronous clock distribution to a plurality of destinations |
November 17, 2009 |
| Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchroni |
| 7619404 |
System and method for testing integrated circuit timing margins |
November 17, 2009 |
| An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between |
| 7619313 |
Multi-chip module and methods |
November 17, 2009 |
| A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. |
| 7619279 |
Three dimensional flash cell |
November 17, 2009 |
| A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures. |
| 7619247 |
Structure for amorphous carbon based non-volatile memory |
November 17, 2009 |
| A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first an |
| 7619184 |
Multi-parameter process and control method |
November 17, 2009 |
| A method and system for generating control settings for a multi-parameter control system. The interdependencies of processing tools and the related effect on semiconductor wafers within a processing tool is factored into a mathematical model that considers desired and measured wafer qual |
| 7618901 |
Process for growing a dielectric layer on a silicon-containing surface using a mixture of N.sub. |
November 17, 2009 |
| This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N.sub.2O) and ozone (O.sub.3). The presence of O.sub.3 in the oxidizing ambiance greatly enhances the oxidation rate compar |
| 7618890 |
Methods for forming conductive structures and structures regarding same |
November 17, 2009 |
| A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal |
| 7618874 |
Methods of forming capacitors |
November 17, 2009 |
| A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening b |
| 7618528 |
Methods and apparatus for electromechanically and/or electrochemically-mechanically removing con |
November 17, 2009 |
| Methods and apparatuses for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate. An apparatus in accordance with one embodiment includes a support member configured to releasably carry a microelectronic substrate and |
| 7617355 |
Parity-scanning and refresh in dynamic memory devices |
November 10, 2009 |
| A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scann |
| 7616504 |
High speed array pipeline architecture |
November 10, 2009 |
| A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first in |
| 7616489 |
Memory array segmentation and methods |
November 10, 2009 |
| The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A |
| 7616482 |
Multi-state memory cell with asymmetric charge trapping |
November 10, 2009 |
| A multi-state NAND memory cell includes two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nit |
| 7616474 |
Offset compensated sensing for magnetic random access memory |
November 10, 2009 |
| An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capac |
| 7616245 |
Active pixel sensor with a diagonal active area |
November 10, 2009 |
| An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the |
| 7616242 |
Linear-logarithmic pixel sensors and gain control circuits therefor |
November 10, 2009 |
| A system and method are disclosed to enlarge the sub-threshold current coefficient ".alpha." of a reset transistor connected to a photodiode in an L-L (Linear Logarithmic) pixel sensor without modifying any semiconductor process parameters. In one embodiment, a coupling capacitor is |
| 7616133 |
Data bus inversion apparatus, systems, and methods |
November 10, 2009 |
| Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed. |
| 7615871 |
Method and apparatus for attaching microelectronic substrates and support members |
November 10, 2009 |
| A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of |
| 7615438 |
Lanthanide yttrium aluminum oxide dielectric films |
November 10, 2009 |
| Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lant |
| 7615164 |
Plasma etching methods and contact opening forming methods |
November 10, 2009 |
| The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first freque |
| 7615119 |
Apparatus for spin coating semiconductor substrates |
November 10, 2009 |
| An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another |
| 7614149 |
Methods for assembling computers |
November 10, 2009 |
| Apparatuses and methods for preventing disengagement of electrical connectors in the assembly of computers. In one embodiment, a computer system includes a chassis, an electrical component contained within the chassis, an electrical connector engaged with a receptacle on the electric |
| 7614027 |
Methods for forming a MRAM with non-orthogonal wiring |
November 3, 2009 |
| The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. Various method embodiments relate to forming a magnetic random access memor |
| 7613070 |
Interleaved input signal path for multiplexed input |
November 3, 2009 |
| System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of ad |
| 7613060 |
Methods, circuits, and systems to select memory regions |
November 3, 2009 |
| Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array |
| 7613031 |
System, apparatus, and method to increase read and write stability of scaled SRAM memory cells |
November 3, 2009 |
| Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias |
| 7613026 |
Apparatus and methods for optically-coupled memory systems |
November 3, 2009 |
| Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the f |
| 7613025 |
Dram cell design with folded digitline architecture and angled active areas |
November 3, 2009 |
| The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 F.sup.2 is disclosed which has a plurality of dual bit active areas, |
| 7613024 |
Local digit line architecture and method for memory devices having multi-bit or low capacitance |
November 3, 2009 |
| A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially |
| 7612816 |
Low power comparator |
November 3, 2009 |
| A comparator with an input stage that selectively powers up an output stage provides an electronic device with a comparator that operates at low power. In an embodiment, an input stage produces a near decision and a true decision, where the near decision is provided to power up an ou |
| 7612620 |
System and method for conditioning differential clock signals and integrated circuit load board |
November 3, 2009 |
| A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of |
| 7612574 |
Systems and methods for defect testing of externally accessible integrated circuit interconnects |
November 3, 2009 |
| Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated |
