| Patent Number |
Title Of Patent |
Date Issued |
| 7470583 |
Method of improved high K dielectric-polysilicon interface for CMOS devices |
December 30, 2008 |
| Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less |
| 7470576 |
Methods of forming field effect transistor gate lines |
December 30, 2008 |
| In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over th |
| 7470563 |
Microelectronic device packages and methods for controlling the disposition of non-conductive ma |
December 30, 2008 |
| A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites acces |
| 7470552 |
Method for production of MRAM elements |
December 30, 2008 |
| Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. F |
| 7470344 |
Chemical dispensing system for semiconductor wafer processing |
December 30, 2008 |
| A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed o |
| 7468922 |
Apparatus and method for dynamically repairing a semiconductor memory |
December 23, 2008 |
| An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as row |
| 7468623 |
Clamp circuit with fuse options |
December 23, 2008 |
| A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The vo |
| 7468559 |
Semiconductor integrated circuit package having electrically disconnected solder balls for mount |
December 23, 2008 |
| Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., "dummy" solder balls, and are used to temporarily hold the die in |
| 7468534 |
Localized masking for semiconductor structure development |
December 23, 2008 |
| Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for pr |
| 7468533 |
Terraced film stack |
December 23, 2008 |
| A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addresse |
| 7468323 |
Method of forming high aspect ratio structures |
December 23, 2008 |
| An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to |
| 7468108 |
Metal layer forming methods and capacitor electrode forming methods |
December 23, 2008 |
| A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer including non-metal components from the precursor. The chemisorbed layer can be treated with an oxidant and the non-metal componen |
| 7468105 |
CMP cleaning composition with microbial inhibitor |
December 23, 2008 |
| An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid |
| 7468104 |
Chemical vapor deposition apparatus and deposition method |
December 23, 2008 |
| A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. A substrate holder is received within the chamber. At least one process chemical inlet to the deposition chamber is included. At |
| 7467334 |
Method for repairing a semiconductor memory |
December 16, 2008 |
| A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and col |
| 7466618 |
Current limiting antifuse programming path |
December 16, 2008 |
| Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive tran |
| 7466615 |
Low voltage data path and current sense amplifier |
December 16, 2008 |
| Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled |
| 7466606 |
Memory device having terminals for transferring multiple types of data |
December 16, 2008 |
| A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information |
| 7466602 |
Method and apparatus for filtering output data |
December 16, 2008 |
| Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option. |
| 7466600 |
System and method for initiating a bad block disable process in a non-volatile memory |
December 16, 2008 |
| A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to |
| 7465999 |
Fully-depleted (FD) (SOI) MOSFET access transistor |
December 16, 2008 |
| A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. |
| 7465983 |
Low tunnel barrier insulators |
December 16, 2008 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7465982 |
Capacitor structures |
December 16, 2008 |
| Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-co |
| 7465650 |
Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry |
December 16, 2008 |
| This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a plug containing polysilicon includes providing a substrate having an opening formed therein. Polysilicon is formed within |
| 7465627 |
Methods of forming capacitors |
December 16, 2008 |
| This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen com |
| 7465616 |
Method of forming a field effect transistor |
December 16, 2008 |
| In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over th |
| 7465608 |
Three-dimensional multichip module |
December 16, 2008 |
| A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chi |
| 7465607 |
Methods of fabrication of lead frame-based semiconductor device packages incorporating at least |
December 16, 2008 |
| Methods of fabrication of lead frame-based semiconductor device packages including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads of the interposer substrat |
| 7465488 |
Bow control in an electronic package |
December 16, 2008 |
| A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to stiffen the substrate adapted to mount one or more dice, one or more dice mounted on the substrate and a molding compound to atta |
| 7465406 |
Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, |
December 16, 2008 |
| In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The antennas have respective pluralities of microwave transmissive openings formed therethrough. At least some of the openings |
| 7464308 |
CAM expected address search testmode |
December 9, 2008 |
| A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected address to determine whether the expected address is defective. The CAM can be tested by applying search data and the expected |
| 7464231 |
Method for self-timed data ordering for multi-data rate memories |
December 9, 2008 |
| A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the successive read operations |
| 7463542 |
Temperature sensing device in an integrated circuit |
December 9, 2008 |
| A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temper |
| 7463520 |
Memory device with variable trim settings |
December 9, 2008 |
| A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is |
| 7463367 |
Estimating overlay error and optical aberrations |
December 9, 2008 |
| Aberration marks, which may be used in conjunction with lenses in optical photolithography systems, may assist in estimating overlay errors and optical aberrations. Aberration marks may include an inner polygon pattern and an outer polygon pattern, wherein each of the inner and outer |
| 7463099 |
Phase detector for reducing noise |
December 9, 2008 |
| The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase diffe |
| 7463052 |
Method and circuit for off chip driver control, and memory device using same |
December 9, 2008 |
| An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to th |
| 7462935 |
Structure and method for forming a capacitively coupled chip-to-chip signaling interface |
December 9, 2008 |
| A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer in |
| 7462559 |
Systems and methods for forming metal-containing layers using vapor deposition processes |
December 9, 2008 |
| A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heteroleptic precursor com |
| 7462534 |
Methods of forming memory circuitry |
December 9, 2008 |
| The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The |
| 7462510 |
Standoffs for centralizing internals in packaging process |
December 9, 2008 |
| A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfa |
| 7462088 |
Method for making large-area FED apparatus |
December 9, 2008 |
| A method is provided for forming and associating a lower section of a large-area field emission device ("FED") that is sealed under a predetermined level of vacuum pressure with an upper section of a large-area FED. The upper section of the FED includes a faceplate. A first conductiv |
| 7461320 |
Memory system and method having selective ECC during low power refresh |
December 2, 2008 |
| A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low powe |
| 7461306 |
Output data compression scheme using tri-state |
December 2, 2008 |
| A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response to |
| 7461286 |
System and method for using a learning sequence to establish communications on a high-speed nons |
December 2, 2008 |
| A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data |
| 7461188 |
Capacitive multidrop bus compensation |
December 2, 2008 |
| The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A |
| 7461139 |
Network computer providing mass storage, broadband access, and other enhanced functionality |
December 2, 2008 |
| A network computer system includes a processor and a memory device coupled to the processor. The memory device contains an embedded operating system that is executed by the processor, the embedded operating system including at least one system parameter. A first reset device coupled to |
| 7460432 |
Sequential access memory with system and method |
December 2, 2008 |
| A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging uni |
| 7460430 |
Memory devices having reduced coupling noise between wordlines |
December 2, 2008 |
| Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak tra |
| 7460429 |
Circuit and method for reducing power in a memory device during standby modes |
December 2, 2008 |
| A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference s |
