| Patent Number |
Title Of Patent |
Date Issued |
| 7473956 |
Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulat |
January 6, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7473662 |
Metal-doped alumina and layers thereof |
January 6, 2009 |
| A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process. |
| 7473645 |
Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor subst |
January 6, 2009 |
| The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature pro |
| 7473644 |
Method for forming controlled geometry hardmasks including subresolution elements |
January 6, 2009 |
| Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their sym |
| 7473637 |
ALD formed titanium nitride films |
January 6, 2009 |
| The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-c |
| 7473615 |
Semiconductor processing methods |
January 6, 2009 |
| The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H.sub.2, with the H.sub.2 being present to a concentration of from about |
| 7473613 |
Terraced film stack |
January 6, 2009 |
| A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause |
| 7473596 |
Methods of forming memory cells |
January 6, 2009 |
| An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The s |
| 7473582 |
Method for fabricating semiconductor component with thinned substrate having pin contacts |
January 6, 2009 |
| A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In |
| 7472392 |
Method for load balancing an n-dimensional array of parallel processing elements |
December 30, 2008 |
| One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of the array includes the processing elements arranged in a plurality of lines and wherein each of the PEs has a local number of |
| 7472248 |
Techniques for generating serial presence detect contents |
December 30, 2008 |
| Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are electronically represented with SPD tokens and rules. When a memory module is identified, a string of needed SPD tokens are acquired |
| 7471565 |
Reducing effects of program disturb in a memory device |
December 30, 2008 |
| A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unsel |
| 7471538 |
Memory module, system and method of making same |
December 30, 2008 |
| A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank |
| 7471535 |
Programable identification circuitry |
December 30, 2008 |
| An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer info |
| 7471228 |
Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal |
December 30, 2008 |
| A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is sw |
| 7471227 |
Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter |
December 30, 2008 |
| In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter. |
| 7471130 |
Graduated delay line for increased clock skew correction circuit operating range |
December 30, 2008 |
| Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated |
| 7470882 |
Reduction in size of column sample and hold circuitry in a CMOS imager |
December 30, 2008 |
| Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over t |
| 7470638 |
Systems and methods for manipulating liquid films on semiconductor substrates |
December 30, 2008 |
| A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diamet |
| 7470635 |
Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuit |
December 30, 2008 |
| This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having |
| 7470632 |
Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge |
December 30, 2008 |
| A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two diffe |
| 7470631 |
Methods for fabricating residue-free contact openings |
December 30, 2008 |
| A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a me |
| 7470628 |
Etching methods |
December 30, 2008 |
| Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching |
| 7470625 |
Method of plasma etching a substrate |
December 30, 2008 |
| A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has |
| 7470606 |
Masking methods |
December 30, 2008 |
| The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The masking material is s |
| 7470590 |
Methods of forming semiconductor constructions |
December 30, 2008 |
| The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication |
| 7470583 |
Method of improved high K dielectric-polysilicon interface for CMOS devices |
December 30, 2008 |
| Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less |
| 7470576 |
Methods of forming field effect transistor gate lines |
December 30, 2008 |
| In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over th |
| 7470563 |
Microelectronic device packages and methods for controlling the disposition of non-conductive ma |
December 30, 2008 |
| A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites acces |
| 7470552 |
Method for production of MRAM elements |
December 30, 2008 |
| Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. F |
| 7470344 |
Chemical dispensing system for semiconductor wafer processing |
December 30, 2008 |
| A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed o |
| 7468922 |
Apparatus and method for dynamically repairing a semiconductor memory |
December 23, 2008 |
| An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as row |
| 7468623 |
Clamp circuit with fuse options |
December 23, 2008 |
| A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The vo |
| 7468559 |
Semiconductor integrated circuit package having electrically disconnected solder balls for mount |
December 23, 2008 |
| Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., "dummy" solder balls, and are used to temporarily hold the die in |
| 7468534 |
Localized masking for semiconductor structure development |
December 23, 2008 |
| Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for pr |
| 7468533 |
Terraced film stack |
December 23, 2008 |
| A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addresse |
| 7468323 |
Method of forming high aspect ratio structures |
December 23, 2008 |
| An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to |
| 7468108 |
Metal layer forming methods and capacitor electrode forming methods |
December 23, 2008 |
| A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer including non-metal components from the precursor. The chemisorbed layer can be treated with an oxidant and the non-metal componen |
| 7468105 |
CMP cleaning composition with microbial inhibitor |
December 23, 2008 |
| An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid |
| 7468104 |
Chemical vapor deposition apparatus and deposition method |
December 23, 2008 |
| A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. A substrate holder is received within the chamber. At least one process chemical inlet to the deposition chamber is included. At |
| 7467334 |
Method for repairing a semiconductor memory |
December 16, 2008 |
| A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and col |
| 7466618 |
Current limiting antifuse programming path |
December 16, 2008 |
| Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive tran |
| 7466615 |
Low voltage data path and current sense amplifier |
December 16, 2008 |
| Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled |
| 7466606 |
Memory device having terminals for transferring multiple types of data |
December 16, 2008 |
| A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information |
| 7466602 |
Method and apparatus for filtering output data |
December 16, 2008 |
| Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option. |
| 7466600 |
System and method for initiating a bad block disable process in a non-volatile memory |
December 16, 2008 |
| A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to |
| 7465999 |
Fully-depleted (FD) (SOI) MOSFET access transistor |
December 16, 2008 |
| A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. |
| 7465983 |
Low tunnel barrier insulators |
December 16, 2008 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7465982 |
Capacitor structures |
December 16, 2008 |
| Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-co |
| 7465650 |
Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry |
December 16, 2008 |
| This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of forming a plug containing polysilicon includes providing a substrate having an opening formed therein. Polysilicon is formed within |
