| Patent Number |
Title Of Patent |
Date Issued |
| RE35764 |
Inverting output driver circuit for reducing electron injection into the substrate |
April 7, 1998 |
| A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the sou |
| RE35750 |
Wordline driver circuit having an automatic precharge circuit |
March 24, 1998 |
| The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of th |
| RE35746 |
Battery package and method using flexible polymer films having a deposited layer of an inorganic |
March 17, 1998 |
| A battery package for a thin battery includes a flexible base film that covers and encloses the battery and a flexible layer of an inorganic material such as silicon nitride, aluminum nitride or aluminum oxide deposited on the base film to encapsulate and seal the battery. The base f |
| RE35420 |
Method of increasing capacitance by surface roughening in semiconductor wafer processing |
January 7, 1997 |
| A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer |
| RE34794 |
Gull-wing zig-zag inline lead package having end-of-package anchoring pins |
November 22, 1994 |
| A semiconductor package having a gull-wing, zig-zag, inline-lead configuration and end-of-package anchoring devices for rigidly affixing the package to a circuit board such that each lead is in compressibe contact with its associated mounting pad on the board. The anchoring devices o |
| RE34425 |
Method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafe |
November 2, 1993 |
| A method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafer or the like. The apparatus includes a polishing head for rotating the wafer under a controlled pressure against a rotating polishing platen. The polishing head is mounted such that the waf |
| D581926 |
Storage device |
December 2, 2008 |
|
| D581413 |
Storage device with slide |
November 25, 2008 |
|
| D580434 |
Mobile card reader |
November 11, 2008 |
|
| D571684 |
Storage device bracelet |
June 24, 2008 |
|
| D566709 |
Storage device |
April 15, 2008 |
|
| D402638 |
Temporary package for semiconductor dice |
December 15, 1998 |
|
| D401567 |
Temporary package for semiconductor dice |
November 24, 1998 |
|
| D394844 |
Temporary package for semiconductor dice |
June 2, 1998 |
|
| 7627796 |
Testing method for permanent electrical removal of an integrated circuit output |
December 1, 2009 |
| An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the integrated circuit includes a disabling device coupled thereto between the input/output terminal and the output driver of the res |
| 7627793 |
Method and apparatus for generating and detecting initialization patterns for high speed DRAM sy |
December 1, 2009 |
| A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals |
| 7627772 |
Fast data access mode in a memory device |
December 1, 2009 |
| A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data |
| 7627737 |
Processing element and method connecting registers to processing logic in a plurality of configu |
December 1, 2009 |
| A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to receive data from |
| 7627568 |
Method and system for updating a search engine database based on popularity of links |
December 1, 2009 |
| A method and a system for maintaining the freshness of a search engine server's database. A popularity parameter is defined, and a popularity value is assigned to each link in the search engine's database. The most popular links are selected for updating the contents stored, or assoc |
| 7626877 |
Low voltage sense amplifier and sensing method |
December 1, 2009 |
| Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is |
| 7626866 |
NAND flash memory programming |
December 1, 2009 |
| A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages. |
| 7626865 |
Charge pump operation in a non-volatile memory device |
December 1, 2009 |
| A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump du |
| 7626626 |
Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in |
December 1, 2009 |
| An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much charge was transferred to the storage gate. The sensed charge is used to obtain at least one signature of the image scene. The |
| 7626416 |
Method and apparatus for high resolution ZQ calibration |
December 1, 2009 |
| A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance |
| 7626269 |
Semiconductor constructions and assemblies, and electronic systems |
December 1, 2009 |
| The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of |
| 7626252 |
Multi-chip electronic package and cooling system |
December 1, 2009 |
| A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the encl |
| 7626238 |
Semiconductor devices having antireflective material |
December 1, 2009 |
| In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the antireflective material layer is annealed at a temperature of greater than about 400.degree. C. A layer of photoresist is formed |
| 7626223 |
Memory structure for reduced floating body effect |
December 1, 2009 |
| Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a |
| 7626219 |
Surround gate access transistors with grown ultra-thin bodies |
December 1, 2009 |
| A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body |
| 7625803 |
Memory devices, electronic systems, and methods of forming memory devices |
December 1, 2009 |
| The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is configured to provide both area and perimeter components of capacitance for capacitive enhancement. The capacitor includes a |
| 7625795 |
Container capacitor structure and method of formation thereof |
December 1, 2009 |
| Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode ("bottom electrodes") of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is ava |
| 7625794 |
Methods of forming zirconium aluminum oxide |
December 1, 2009 |
| A dielectric layer having atomic layer deposited zirconium aluminum oxide and a method of fabricating such a dielectric layer may produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO.sub.2. The zirconium aluminum oxide may be form |
| 7625776 |
Methods of fabricating intermediate semiconductor structures by selectively etching pockets of i |
December 1, 2009 |
| A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut struc |
| 7625766 |
Methods of forming carbon nanotubes and methods of fabricating integrated circuitry |
December 1, 2009 |
| A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated cir |
| 7625694 |
Selective provision of a diblock copolymer material |
December 1, 2009 |
| Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an embodiment, the DBCP film is deposited on the circuit layer to be etched. Then the DCBP film is confined to define an area of interest in |
| 7625641 |
Method of forming a crystalline phase material |
December 1, 2009 |
| A method of forming a crystalline phase material includes: providing stress inducing material within or operatively adjacent a material of a first crystalline phase; and annealing under conditions effective to transform the material to a second crystalline phase. The stress inducing |
| 7625495 |
Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planari |
December 1, 2009 |
| Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressi |
| 7625460 |
Multifrequency plasma reactor |
December 1, 2009 |
| A multifrequency plasma reactor includes first, second and third power generators operably coupled to at least one of an upper and lower electrode for generating power signals. The plasma reactor further includes a controller for selectively activating the power generators according |
| 7624310 |
System and method for initializing a memory system, and memory device and processor-based system |
November 24, 2009 |
| Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of |
| 7624211 |
Method for bus width negotiation of data storage devices |
November 24, 2009 |
| There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If |
| 7624180 |
Mixed enclave operation in a computer network |
November 24, 2009 |
| A method is disclosed for mixed enclave operation of a computer network with users employing a multi-level network security interface and users without any network security interface. Either the network security user selects or the network security interface automatically selects whether |
| 7623568 |
System and method for testing a modem |
November 24, 2009 |
| A modem tester includes a signal reporting circuit which can report signals received from the modem of the computer. To test the operation of the modem in the computer, test data can be sent from the modem tester to the modem in the computer and test data can be received by the modem |
| 7623392 |
Method and system for controlling refresh to avoid memory cell data losses |
November 24, 2009 |
| A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter |
| 7623365 |
Memory device interface methods, apparatus, and systems |
November 24, 2009 |
| Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die |
| 7622990 |
Amplifiers, methods of increasing current gain in amplifiers, and imaging devices |
November 24, 2009 |
| An amplifier includes a differential stage including a differential pair of transistors of a first conductivity type, the differential pair having gates, first and second inputs to the amplifier respectively including the gates of the differential pair; a current sum branch coupled to th |
| 7622986 |
High performance input receiver circuit for reduced-swing inputs |
November 24, 2009 |
| An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain "buffered" output signals therefrom with symmetrical rising and falling delays, and without additional current dissipation over previous |
| 7622970 |
Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequen |
November 24, 2009 |
| A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effec |
| 7622969 |
Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock |
November 24, 2009 |
| Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal and output a delayed clock signal. The delay locked loop may also comprise a feedback loop including a frequency divider o |
| 7622957 |
Pseudo-differential output driver with high immunity to noise and jitter |
November 24, 2009 |
| Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and pro |
| 7622908 |
Built-in system and method for testing integrated circuit timing parameters |
November 24, 2009 |
| A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus terminals and a data strobe terminal of the memory device responsive to respective clock signals. The clock signal are generated by |
