| Patent Number |
Title Of Patent |
Date Issued |
| 7479650 |
Method of manufacture of programmable conductor memory |
January 20, 2009 |
| Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom electrode in contact with a conductive region in a semiconductor substrate, a glass electrolyte layer that forms the body of |
| 7479440 |
Method of forming an isolation structure that includes forming a silicon layer at a base of the |
January 20, 2009 |
| A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon |
| 7479413 |
Method for fabricating semiconductor package with circuit side polymer layer |
January 20, 2009 |
| A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized |
| 7479206 |
Apparatus for in-situ optical endpointing on web-format planarizing machines in mechanical or ch |
January 20, 2009 |
| Polishing pads, planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies. The polishing pads, for example, can be web-format pads, and the planarizing machines can be web-format machines. In a typical appl |
| 7478032 |
Method and system for selecting compatible processors to add to a multiprocessor computer |
January 13, 2009 |
| A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and |
| 7477570 |
Sequential access memory with system and method |
January 13, 2009 |
| A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging uni |
| 7477557 |
256 Meg dynamic random access memory |
January 13, 2009 |
| A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual a |
| 7477556 |
256 Meg dynamic random access memory |
January 13, 2009 |
| A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual a |
| 7477554 |
Data retention kill function |
January 13, 2009 |
| A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and comparing sensed operational parameters to the authorized operating parameters. Access to data stored within the memory devic |
| 7477542 |
Split gate flash memory cell with ballistic injection |
January 13, 2009 |
| A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated fro |
| 7477306 |
Method and apparatus for improving pixel output swing in imager sensors |
January 13, 2009 |
| A bias readout circuit is disclosed for use in reading out a pixel of an imager system. The bias readout circuit includes a circuit portion which mirrors an output and bias transistor of a pixel to amplify an output signal produced by a pixel and increase the dynamic range of the pixel |
| 7477304 |
Two narrow band and one wide band color filter for increasing color image sensor sensitivity |
January 13, 2009 |
| A color filter to increase the low light sensitivity of an image sensor. The color filter has two narrow band color filters and one wide band filter. Also disclosed is a unique way of processing a tri-stimulus signal to dynamically adjust color contrast depending on the illumination |
| 7477298 |
Anti-eclipsing circuit for image sensors |
January 13, 2009 |
| An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection circuit for controllably coupling the clamping circuit output to the output of the pixel. The clamping circuit includes a source |
| 7476955 |
Die package having an adhesive flow restriction area |
January 13, 2009 |
| A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that |
| 7476933 |
Vertical gated access transistor |
January 13, 2009 |
| According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The |
| 7476927 |
Scalable multi-functional and multi-level nano-crystal non-volatile memory device |
January 13, 2009 |
| A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two layers such as HfO.sub.2 and LaAlO.sub.3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this la |
| 7476925 |
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulato |
January 13, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7476836 |
Multi-point correlated sampling for image sensors |
January 13, 2009 |
| An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating amplifier during sampling periods. An integrator circuit is provided for integrating PPS pixel charges received via a column line, |
| 7476588 |
Methods of forming NAND cell units with string gates of various widths |
January 13, 2009 |
| Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O.sub.2 to extend a |
| 7476586 |
NOR flash memory cell with high storage density |
January 13, 2009 |
| Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain regi |
| 7476556 |
Systems and methods for plasma processing of microfeature workpieces |
January 13, 2009 |
| Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a |
| 7476305 |
Recovery system for platinum plating bath |
January 13, 2009 |
| A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation system for platinum plating at low current densities. The oxidizing system reoxidizes Pt.sup.+2 ions, which are typically form |
| 7476277 |
Apparatus for improving stencil/screen print quality |
January 13, 2009 |
| A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In |
| 7475137 |
Methods of operating portable computerized device with network security |
January 6, 2009 |
| A multi-level network security system is disclosed for a computer host device coupled to at least one computer network. The system including a secure network interface Unit (SNIU) contained within a communications stack of the computer device that operates at a user layer communications |
| 7474846 |
Method and apparatus of determining the best focus position of a lens |
January 6, 2009 |
| A method and apparatus for accurately auto focusing a lens of an imaging device. An imaged scene is split into an array of zones. The minimum and maximum sharpness score for each zone is determined over a plurality of lens positions. A histogram of the lens positions of the corresponding |
| 7474560 |
Non-volatile memory with both single and multiple level cells |
January 6, 2009 |
| Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed between and coupled to a select gate and a multiple level non-volatile memory cell. Various embodiments include structure, process, |
| 7473956 |
Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulat |
January 6, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7473662 |
Metal-doped alumina and layers thereof |
January 6, 2009 |
| A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process. |
| 7473645 |
Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor subst |
January 6, 2009 |
| The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature pro |
| 7473644 |
Method for forming controlled geometry hardmasks including subresolution elements |
January 6, 2009 |
| Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their sym |
| 7473637 |
ALD formed titanium nitride films |
January 6, 2009 |
| The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface using a titanium-c |
| 7473615 |
Semiconductor processing methods |
January 6, 2009 |
| The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H.sub.2, with the H.sub.2 being present to a concentration of from about |
| 7473613 |
Terraced film stack |
January 6, 2009 |
| A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause |
| 7473596 |
Methods of forming memory cells |
January 6, 2009 |
| An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The s |
| 7473582 |
Method for fabricating semiconductor component with thinned substrate having pin contacts |
January 6, 2009 |
| A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In |
| 7472392 |
Method for load balancing an n-dimensional array of parallel processing elements |
December 30, 2008 |
| One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of the array includes the processing elements arranged in a plurality of lines and wherein each of the PEs has a local number of |
| 7472248 |
Techniques for generating serial presence detect contents |
December 30, 2008 |
| Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are electronically represented with SPD tokens and rules. When a memory module is identified, a string of needed SPD tokens are acquired |
| 7471565 |
Reducing effects of program disturb in a memory device |
December 30, 2008 |
| A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unsel |
| 7471538 |
Memory module, system and method of making same |
December 30, 2008 |
| A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank |
| 7471535 |
Programable identification circuitry |
December 30, 2008 |
| An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer info |
| 7471228 |
Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal |
December 30, 2008 |
| A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is sw |
| 7471227 |
Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter |
December 30, 2008 |
| In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second stage. The first and second stages are configured to share a sub-ADC and a sub-digital-to-analog converter. |
| 7471130 |
Graduated delay line for increased clock skew correction circuit operating range |
December 30, 2008 |
| Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement, allowing a reduced circuit implementation and improved lock characteristics. These graduated |
| 7470882 |
Reduction in size of column sample and hold circuitry in a CMOS imager |
December 30, 2008 |
| Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of the CSH circuitry is reduced by providing a plurality of pairs of sampling and reference capacitors in a vertical stack over t |
| 7470638 |
Systems and methods for manipulating liquid films on semiconductor substrates |
December 30, 2008 |
| A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diamet |
| 7470635 |
Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuit |
December 30, 2008 |
| This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having |
| 7470632 |
Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge |
December 30, 2008 |
| A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer comprising oxygen and dopant which become part of the deposited doped silicon dioxide. The feeding is over at least two diffe |
| 7470631 |
Methods for fabricating residue-free contact openings |
December 30, 2008 |
| A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a me |
| 7470628 |
Etching methods |
December 30, 2008 |
| Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching |
| 7470625 |
Method of plasma etching a substrate |
December 30, 2008 |
| A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has |
