| Patent Number |
Title Of Patent |
Date Issued |
| 7486550 |
Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate me |
February 3, 2009 |
| A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic or |
| 7486530 |
Method of comparison between cache and data register for non-volatile memory |
February 3, 2009 |
| A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a |
| 7485971 |
Electronic device package |
February 3, 2009 |
| An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to which the die will be fixed. The die is placed on the discrete die attach. The die attach, in an embodiment, is an epoxy resin |
| 7485969 |
Stacked microelectronic devices and methods for manufacturing microelectronic devices |
February 3, 2009 |
| Stacked microelectronic devices and methods for manufacturing such devices. An embodiment of a microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side, a first te |
| 7485961 |
Approach to avoid buckling in BPSG by using an intermediate barrier layer |
February 3, 2009 |
| A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed |
| 7485948 |
Front-end processing of nickel plated bond pads |
February 3, 2009 |
| A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. |
| 7485942 |
Films deposited at glancing incidence for multilevel metallization |
February 3, 2009 |
| Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstruct |
| 7485904 |
Pixel with strained silicon layer for improving carrier mobility and blue response in imagers |
February 3, 2009 |
| An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices. |
| 7485836 |
Row driver for selectively supplying operating power to imager pixel |
February 3, 2009 |
| An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating volt |
| 7485587 |
Method of making a semiconductor device having improved contacts |
February 3, 2009 |
| A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer |
| 7485562 |
Method of making multichip wafer level packages and computing systems incorporating same |
February 3, 2009 |
| The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and in |
| 7485548 |
Die loss estimation using universal in-line metric (UILM) |
February 3, 2009 |
| A system predicts die loss for a semiconductor wafer by using a method referred to as universal in-line metric (UILM). A wafer inspection tool detects defects on the wafer and identifies the defects by various defect types. The UILM method applies to various ways of classification of the |
| 7485544 |
Strained semiconductor, devices and systems and methods of formation |
February 3, 2009 |
| In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to |
| 7485528 |
Method of forming memory devices by performing halogen ion implantation and diffusion processes |
February 3, 2009 |
| Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a |
| 7485526 |
Floating-gate structure with dielectric component |
February 3, 2009 |
| Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. |
| 7485513 |
One-device non-volatile random access memory cell |
February 3, 2009 |
| One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion |
| 7485504 |
Stable PD-SOI devices and methods |
February 3, 2009 |
| One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si--Ge) |
| 7485497 |
Integrated circuit cooling and insulating device and method |
February 3, 2009 |
| A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a |
| 7484142 |
System and method for testing a memory for a memory failure exhibited by a failing memory |
January 27, 2009 |
| A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence |
| 7483334 |
Interleaved input signal path for multiplexed input |
January 27, 2009 |
| System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of ad |
| 7483333 |
Memory device and method having banks of different sizes |
January 27, 2009 |
| A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored is determined by ei |
| 7483330 |
Power efficient memory and cards |
January 27, 2009 |
| A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard devi |
| 7483315 |
Techniques for implementing accurate operating current values stored in a database |
January 27, 2009 |
| Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system p |
| 7483311 |
Erase operation in a flash memory device |
January 27, 2009 |
| A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells |
| 7483305 |
Method, apparatus and system relating to automatic cell threshold voltage measurement |
January 27, 2009 |
| Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells, a pre-charge bit line reference circuit, and comparator and latch circuitry. If the r |
| 7483286 |
Semiconductor memory device with high permeability lines interposed between adjacent transmissio |
January 27, 2009 |
| A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the |
| 7483067 |
Column-parallel sigma-delta analog-to-digital conversion for imagers |
January 27, 2009 |
| A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that do not rely on the ratio of the reset and pixel voltage levels being sensed. The sensing circuit includes a regulation branch based on a reference voltage common across multiple columns of |
| 7482855 |
Circuit and method for stable fuse detection |
January 27, 2009 |
| A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal |
| 7482833 |
Method and circuit for controlling pin capacitance in an electronic device |
January 27, 2009 |
| A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-st |
| 7482798 |
Regulated internal power supply and method |
January 27, 2009 |
| A regulated internal power supply and method are provided. According to various embodiments, a regulated internal power supply system includes a DC to DC converter adapted to connect to an external supply voltage. The converter is further adapted to increase voltage level above a level o |
| 7482702 |
Semiconductor component sealed on five sides by polymer sealing layer |
January 27, 2009 |
| A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A me |
| 7482687 |
Etch stop in a damascene interconnect structure |
January 27, 2009 |
| An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low |
| 7482653 |
Non-volatile memory with carbon nanotubes |
January 27, 2009 |
| Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For so |
| 7482651 |
Enhanced multi-bit non-volatile memory device with resonant tunnel barrier |
January 27, 2009 |
| A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO.sub.3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge |
| 7482630 |
NAND memory arrays |
January 27, 2009 |
| A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate and is connected in series between the source select gate and the drain select gate. A dra |
| 7482284 |
Deposition methods for forming silicon oxide layers |
January 27, 2009 |
| A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds. |
| 7482239 |
Methods of forming integrated circuitry |
January 27, 2009 |
| In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor electrode forming layer to within the opening over at least upper portions of sidewalls of the opening. The spacing layer is formed |
| 7482229 |
DRAM cells with vertical transistors |
January 27, 2009 |
| The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pill |
| 7482190 |
Micromechanical strained semiconductor by wafer bonding |
January 27, 2009 |
| One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are formed in a surface of a silicon substrate using a Local Oxidation of Silicon (LOCOS) process, and a silicon membrane is bonded t |
| 7482176 |
Etch mask and method of forming a magnetic random access memory structure |
January 27, 2009 |
| A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer |
| 7482037 |
Methods for forming niobium and/or vanadium containing layers using atomic layer deposition |
January 27, 2009 |
| A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more precursor compounds that include niobium and/or vanadium and using an atomic la |
| 7481887 |
Apparatus for controlling gas pulsing in processes for depositing materials onto micro-device wo |
January 27, 2009 |
| An apparatus for depositing materials onto a micro-device workpiece includes a gas source system configured to provide a first precursor, a second precursor, and a purge gas. The apparatus can also include a valve assembly coupled to the gas source system. The valve assembly is confi |
| 7480792 |
Memory modules having accurate operating parameters stored thereon and methods for fabricating a |
January 20, 2009 |
| Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating parameters for specific memory device |
| 7480762 |
Erase block data splitting |
January 20, 2009 |
| A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into |
| 7480203 |
Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM |
January 20, 2009 |
| A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of |
| 7480202 |
High speed array pipeline architecture |
January 20, 2009 |
| A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first in |
| 7480199 |
Method for low power refresh of a dynamic random access memory using a slower refresh rate than |
January 20, 2009 |
| A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are |
| 7480195 |
Internal data comparison for memory testing |
January 20, 2009 |
| Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sense |
| 7480186 |
NROM flash memory with self-aligned structural charge separation |
January 20, 2009 |
| A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride layer, is comprised of two sections that each have structurally defined and separated charge trapping regions. A charge is sto |
| 7480185 |
Ballistic injection NROM flash memory |
January 20, 2009 |
| A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The nitride storage regions are |
