| Patent Number |
Title Of Patent |
Date Issued |
| 7498240 |
Microfeature workpieces, carriers, and associated methods |
March 3, 2009 |
| Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can include temporarily attaching the microfeature workpiece to a carrier with a releasable connector, wherein the connector is at least |
| 7498231 |
Multiple data state memory cell |
March 3, 2009 |
| A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second |
| 7498230 |
Magnesium-doped zinc oxide structures and methods |
March 3, 2009 |
| Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent c |
| 7498057 |
Deposition methods |
March 3, 2009 |
| A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the |
| 7497958 |
Methods of forming capacitors |
March 3, 2009 |
| The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a |
| 7497825 |
Data download to imager chip using image sensor as a receptor |
March 3, 2009 |
| An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to control the imaging operations. The data-input can be based upon variations in light color, value, intensity, and patterning, or an |
| 7497005 |
Method for forming an inductor |
March 3, 2009 |
| A method of fabricating an inductor includes selecting a substrate, depositing a layer of magnetic material on the substrate, depositing an insulating layer on the magnetic material layer, forming a inductor pattern from gold on the insulating layer, depositing a second insulating la |
| 7496235 |
Scan line to block re-ordering buffer for image compression |
February 24, 2009 |
| A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing mode, which causes the data to be stored in a line-by-line manner. Prior to receiving the last line of input data, the store |
| 7495966 |
Memory voltage cycle adjustment |
February 24, 2009 |
| The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includ |
| 7495964 |
Method and apparatus for sensing flash memory using delta sigma modulation |
February 24, 2009 |
| A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a |
| 7495487 |
Delay-locked loop (DLL) system for determining forward clock path delay |
February 24, 2009 |
| A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock |
| 7495316 |
Methods of forming conductive vias and methods of forming multichip modules including such condu |
February 24, 2009 |
| A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hol |
| 7495277 |
Memory circuitry |
February 24, 2009 |
| The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell elec |
| 7494939 |
Methods for forming a lanthanum-metal oxide dielectric layer |
February 24, 2009 |
| Atomic layer deposited lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed b |
| 7494925 |
Method for making through-hole conductors for semiconductor substrates |
February 24, 2009 |
| A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semic |
| 7494922 |
Small electrode for phase change memories |
February 24, 2009 |
| A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Furt |
| 7494910 |
Methods of forming semiconductor package |
February 24, 2009 |
| The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes meth |
| 7494894 |
Protection in integrated circuits |
February 24, 2009 |
| A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and |
| 7494889 |
Method of manufacturing an interposer including at least one passive element at least partially |
February 24, 2009 |
| An interposer for assembly with a semiconductor die and methods of manufacture are disclosed. The interposer may include at least one passive element at least partially defined by at least one recess formed in at least one dielectric layer of the interposer. The at least one recess m |
| 7494873 |
Memory utilizing oxide-nitride nanolaminates |
February 24, 2009 |
| Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate i |
| 7494750 |
Reticles |
February 24, 2009 |
| The invention includes reticles and methods of forming reticles. In one aspect, a reticle can include a quartz-containing substrate, an attenuating layer, and an antireflective structure between the attenuating layer and the quartz-containing substrate. The invention can also include |
| 7493442 |
Multiple segment data object management |
February 17, 2009 |
| A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index table objects containing defining information about the data objects in which the data are stored, such as the state, index table |
| 7492652 |
Apparatus and method for repairing a semiconductor memory |
February 17, 2009 |
| An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A |
| 7492376 |
Graphics resampling system and method for use thereof |
February 17, 2009 |
| A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample |
| 7492287 |
Two-bit tri-level forced transition encoding |
February 17, 2009 |
| An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are convert |
| 7492196 |
Low injection charge pump |
February 17, 2009 |
| A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output of the charge pump |
| 7492086 |
Low work function emitters and method for production of FED's |
February 17, 2009 |
| According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an evacuated space between the anode and the cathode; an emitter located on the cathode opposite the phosphor; wherein the emitter c |
| 7492042 |
Integrated circuit cooling and insulating device and method |
February 17, 2009 |
| A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a |
| 7492039 |
Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, |
February 17, 2009 |
| An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined dist |
| 7492030 |
Techniques to create low K ILD forming voids between metal lines |
February 17, 2009 |
| One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After |
| 7492027 |
Reduced crosstalk sensor and method of formation |
February 17, 2009 |
| Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating trench among pixels or other active areas of a semiconductor device. The trench extends through the substrate to the base lay |
| 7491995 |
DRAM with nanofin transistors |
February 17, 2009 |
| One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second |
| 7491963 |
Non-volatile memory structure |
February 17, 2009 |
| A non-volatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead of storing or removing electrons from a floating gate, the programmable conductor is switched between its low and high resistive |
| 7491962 |
Resistance variable memory device with nanoparticle electrode and method of fabrication |
February 17, 2009 |
| A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of t |
| 7491650 |
Etch compositions and methods of processing a substrate |
February 17, 2009 |
| The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH.sub.4F and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one |
| 7491641 |
Method of forming a conductive line and a method of forming a conductive contact adjacent to and |
February 17, 2009 |
| This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative materi |
| 7491636 |
Methods for forming flexible column die interconnects and resulting structures |
February 17, 2009 |
| A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in |
| 7491608 |
Vertical transistor with horizontal gate layers |
February 17, 2009 |
| Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic array in a high density field programmable logic array (FPLA). The transistor is a field-effe |
| 7491602 |
Structures and methods for improved capacitor cells in integrated circuits |
February 17, 2009 |
| Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive layer of a semiconductor structure. A layer of an inhibiting substance may be used to inhibit a net flow of atoms so as to |
| 7491570 |
Die package having an adhesive flow restriction area |
February 17, 2009 |
| A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element. A second embodiment has a transparent element with an adhesive flow restriction area formed as a plurality of trenches that |
| 7490211 |
Memory hub with integrated non-volatile memory |
February 10, 2009 |
| A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory con |
| 7490210 |
System and method for processor with predictive memory retrieval assist |
February 10, 2009 |
| A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline |
| 7490190 |
Method and system for local memory addressing in single instruction, multiple data computer syst |
February 10, 2009 |
| A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random access memory ("SRAM") devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM devic |
| 7489875 |
System and method for multiple bit optical data transmission in memory systems |
February 10, 2009 |
| The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of light so that each pulse of optical signals can represent more than a single bit of data. An optical transmitter comprises |
| 7489587 |
Semiconductor memory device capable of controlling clock cycle time for reduced power consumptio |
February 10, 2009 |
| Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjust the timing relationship between the first signal and an internal signal. |
| 7489575 |
Noise resistant small signal sensing circuit for a memory device |
February 10, 2009 |
| Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a |
| 7489569 |
Reconstruction of signal timing in integrated circuits |
February 10, 2009 |
| Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the |
| 7489568 |
Delay stage-interweaved analog DLL/PLL |
February 10, 2009 |
| A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow f |
| 7489564 |
256 Meg dynamic random access memory |
February 10, 2009 |
| A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual a |
| 7489556 |
Method and apparatus for generating read and verify operations in non-volatile memories |
February 10, 2009 |
| Method and apparatus for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, and a voltage converter, all operably coupled to a current sum node. The first current source generates a first current |
