| Patent Number |
Title Of Patent |
Date Issued |
| 7508016 |
CMOS imager having on-chip ROM |
March 24, 2009 |
| A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circ |
| 7507672 |
Plasma etching system and method |
March 24, 2009 |
| A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma etching of the devic |
| 7506226 |
System and method for more efficiently using error correction codes to facilitate memory device |
March 17, 2009 |
| A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is "0," the test data bits are all "0," and if the received |
| 7506146 |
Fast and compact circuit for bus inversion |
March 17, 2009 |
| A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the |
| 7506126 |
Detection circuit for mixed asynchronous and synchronous memory operation |
March 17, 2009 |
| A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal i |
| 7505357 |
Column/row redundancy architecture using latches programmed from a look up table |
March 17, 2009 |
| A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address |
| 7505341 |
Low voltage sense amplifier and sensing method |
March 17, 2009 |
| Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is |
| 7505330 |
Phase-change random access memory employing read before write for resistance stabilization |
March 17, 2009 |
| An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has t |
| 7505323 |
Programming memory devices |
March 17, 2009 |
| A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the |
| 7505317 |
Method, apparatus, and system for providing initial state random access memory |
March 17, 2009 |
| A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comp |
| 7505309 |
Static RAM memory cell with DNR chalcogenide devices and method of forming |
March 17, 2009 |
| An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting differential negative resistance characteristics. One of the two devices serves as the load of the other. A switch is provided to |
| 7504767 |
Electrode structures, display devices containing the same |
March 17, 2009 |
| An electrode structure for a display device comprising a gate electrode proximate to an emitter and a focusing electrode separated from the gate electrode by an insulating layer containing a ridge are provided. When the focusing electrode is an aperture-type electrode, the ridge protrude |
| 7504730 |
Memory elements |
March 17, 2009 |
| Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as |
| 7504687 |
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulato |
March 17, 2009 |
| Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second |
| 7504685 |
Oxide epitaxial isolation |
March 17, 2009 |
| Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming at least one first recess through the first oxide layer to the strained substrate, and forming at least one vertical epitaxi |
| 7504674 |
Electronic apparatus having a core conductive structure within an insulating layer |
March 17, 2009 |
| Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H.sub.2 |
| 7504310 |
Semiconductors bonded on glass substrates |
March 17, 2009 |
| A method includes providing a glass substrate and bonding a semiconductor layer to the glass substrate. The semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. |
| 7504298 |
Method for forming memory cell and device |
March 17, 2009 |
| A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells |
| 7504285 |
Carrierless chip package for integrated circuit devices, and methods of making same |
March 17, 2009 |
| Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductivel |
| 7504284 |
Microelectronic device packages, stacked microelectronic device packages, and methods for manufa |
March 17, 2009 |
| A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made |
| 7503046 |
Method of obtaining interleave interval for two data values |
March 10, 2009 |
| A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2.sup.z-n may be used to represent the value of y, includes generating a key including the reverse bit order of a serially indexed count from 0 to |
| 7503002 |
Text based markup language resource interface |
March 10, 2009 |
| A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference documents, install system drivers and perform various system utilities. The interface can reference optical drivers, hard disk dr |
| 7502659 |
Sorting a group of integrated circuit devices for those devices requiring special testing |
March 10, 2009 |
| A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing includes storing fabrication deviation data, probe data, and test data in association with |
| 7502058 |
Imager with tuned color filter |
March 10, 2009 |
| An optimized color filter array is formed in, above or below a one or more damascene layers. The color filter array includes filter regions which are configured to optimize the combined optical properties of the layers of the device to maximize the intensity of the particular wavelength |
| 7501971 |
Analog-to-digital converter with resistor ratio |
March 10, 2009 |
| Various embodiments disclose apparatus, systems, and methods operating with a first circuit branch with transistors coupled in series between first and second supply nodes, and a second circuit branch with second transistors coupled in series between the first and second supply nodes. |
| 7501963 |
Balanced data bus inversion |
March 10, 2009 |
| A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the "balance" of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bit |
| 7501691 |
Trench insulation structures including an oxide liner and oxidation barrier |
March 10, 2009 |
| A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon |
| 7501684 |
Methods of forming semiconductor constructions |
March 10, 2009 |
| The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly rela |
| 7501676 |
High density semiconductor memory |
March 10, 2009 |
| A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active area |
| 7501672 |
Method and structure for a self-aligned silicided word line and polysilicon plug during the form |
March 10, 2009 |
| A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive en |
| 7501329 |
Wafer gettering using relaxed silicon germanium epitaxial proximity layers |
March 10, 2009 |
| One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon german |
| 7501313 |
Method of making semiconductor BGA package having a segmented voltage plane |
March 10, 2009 |
| A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive layer, which is, in turn, connected to a dielectric layer carrying conductive traces of the electrical connection layer. Th |
| 7501309 |
Standoffs for centralizing internals in packaging process |
March 10, 2009 |
| A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfa |
| 7500858 |
Portable electronic device with built-in terminal cover structure |
March 10, 2009 |
| A portable electronic device including a housing having a receptacle for at least one semiconductor die, a terminal carried by the housing and operably coupled to the at least one semiconductor die, an attached cover, and operation indicators. In one position, the cover encompasses a |
| 7499983 |
Web dispatch service |
March 3, 2009 |
| A system and method for accessing an application server includes sending a service command from a requestor to a dispatch server, processing the service command on the dispatch server, translating the service command on the dispatch server into an application request to the application |
| 7499362 |
Techniques for storing accurate operating current values |
March 3, 2009 |
| A technique for storing accurate operating current values using programmable elements on memory devices. More specifically, programmable elements, such as antifuses, located on a memory device are programmed with measured operating current values corresponding to the memory device, d |
| 7499330 |
Programming method for NAND EEPROM |
March 3, 2009 |
| A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array |
| 7499329 |
Flash memory array using adjacent bit line as source |
March 3, 2009 |
| A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and |
| 7499302 |
Noise reduction in a CAM memory cell |
March 3, 2009 |
| A dynamic CAM cell has features that reduce the effect of noise within a CAM array. By shielding the matchline from the wordline, noise transmitted from the matchline to the wordline is reduced. By placing the searchline equally distant from a bitline and the bitline complement, the |
| 7498875 |
Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers |
March 3, 2009 |
| The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-n |
| 7498759 |
Semiconductor wafer processing accelerometer |
March 3, 2009 |
| An end effector of a robot tool that includes accelerometers and methods to sense end effector motion. A semiconductor substrate or similar object may be supported by the end effector. Motion of the end effector and associated substrate movement may be transduced and sampled according to |
| 7498675 |
Semiconductor component having plate, stacked dice and conductive vias |
March 3, 2009 |
| A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back sid |
| 7498670 |
Semiconductor structures having electrophoretically insulated vias |
March 3, 2009 |
| Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The |
| 7498647 |
Packaged microelectronic imagers and methods of packaging microelectronic imagers |
March 3, 2009 |
| Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrat |
| 7498629 |
Stud electrode and process for making same |
March 3, 2009 |
| A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also |
| 7498606 |
Microelectronic imaging units and methods of manufacturing microelectronic imaging units |
March 3, 2009 |
| Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated ima |
| 7498265 |
Epitaxial silicon growth |
March 3, 2009 |
| Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A |
| 7498260 |
Pass through via technology for use during the manufacture of a semiconductor device |
March 3, 2009 |
| A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coup |
| 7498258 |
Through-hole conductors for semiconductor substrates and method for making same |
March 3, 2009 |
| A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to a second side of the semiconductor substrate and plating the inner surface of the semic |
| 7498247 |
Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics |
March 3, 2009 |
| The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Fo |
